technical manual cmos 32 - bit single chip microcomputer s1c33e08
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requir - ing high level reliability, such as medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this mate - rial will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. the epson s1c33e08 incorporates mp3 technology of which thomson sa in france holds the patent. manufacturers using the epson s1c33e08 to develop mp3 products must pay royalties to thomson sa in order to procure the license for the mp3 technology. ? seiko epson corporation 2007, all rights reserved.
devices s1 c 33209 f 00e1 packing specifications 00 : besides tape & reel 0a : tcp bl 2 directions 0b : tape & reel back 0c : tcp br 2 directions 0d : tcp bt 2 directions 0e : tcp bd 2 directions 0f : tape & reel front 0g : tcp bt 4 directions 0h : tcp bd 4 directions 0j : tcp sl 2 directions 0k : tcp sr 2 directions 0l : tape & reel left 0m : tcp st 2 directions 0n : tcp sd 2 directions 0p : tcp st 4 directions 0q : tcp sd 4 directions 0r : tape & reel right 99 : specs not fixed specification package d: die form; f: qfp, b: bga model number model name c: microcomputer, digital products product classification s1: semiconductor development tools s5u1 c 33000 h2 1 packing specifications 00: standard packing version 1: version 1 tool type hx : ice dx : evaluation board ex : rom emulation board mx : emulation memory for external rom tx : a socket for mounting cx : compiler package sx : middleware package corresponding model number 33l01: for s1c33l01 tool classification c: microcomputer use product classification s5u1: development tool for semiconductor products 00 00 configuration of product number
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock s1c33e08 technical manual i s1c33e08 specifications i.1 overvie w i.2 block diagra m i.3 pin d escriptio n i.4 power suppl y i.5 cpu core and bus architecture i.6 memory ma p i.7 electrical characteristic s i.8 basic external wiring diagra m i.9 precautions on mountin g ii bus modules ii.1 high-speed dma (hsdma ) ii.2 intelligent dma (idma ) ii.3 sram controller (sramc ) ii.4 sdram controller (sdramc ) iii peripheral modules 1 (system) iii.1 clock management unit (cmu) iii.2 interrupt controller (itc ) iii.3 real-time clock (rtc ) iii.4 misc registers iv peripheral modules 2 (timers) iv. 1 16 -bit timers (t16 ) iv. 2 watchdog timer (wdt ) v peripheral modules 3 (interface) v. 1 general-purpose serial interface (efsio ) v. 2 serial peripheral interface (spi) v. 3 direction control serial interface (dcsio) v. 4 card interface (card ) v. 5 i 2 s interface (i 2 s) vi peripheral modules 4 (ports) vi.1 general-purpose i/o ports (gpio ) vi.2 extended general-purpose i/o ports (egpio ) vii peripheral modules 5 (analog) vii.1 a/d converter (adc ) viii peripheral modules 6 (lcd) viii.1 lcd controller (lcdc) viii.2 ivram and ivram arbiter ix peripheral modules 7 (usb) ix.1 usb function controller (usb) x peripheral modules 8 (mp3) x.1 mp3 decoder (mp3) appendix a i/o map b differences between c 33 pe core and other c33 core c development tools d boot e summary of precautions f supplementary description for clock control
preface s1c33e08 technical manual epson i application this manual describes the hardware functions and control registers of the s 1c33e08 or seiko epson s risc-type 32 -bit microcomputer, and precautions to observe when designing the application system for the microcomputer. since this manual is written for those who design applications and circuits, knowledge of embedded-type micro - computers and the functionality and control of general peripheral circuits is required to understand the contents of this manual. organization of the manual i. s 1c33e08 specifications this chapter outlines the s 1c33e08 and describes the pin functions, and electrical characteristics. also noise protection and other precautions to be taken when mounting the chip on the circuit board are included. ii. bus module this chapter describes the modules to control dma and the bus. iiiCx peripheral modules these chapters describe each peripheral module embedded in the s 1c33e08. appendix provides a list of control registers built into the s 1c33e08 and other additional information. notational conventions for control bits and addresses this manual describes some control bits as follows: example: 16 -bit timer run/stop control bits prun x (d0/0x300786 + 8? x ) x in this example represents a timer number ( 0 to 5 ). timer 0 to timer 5 have control bits for each timer that have the same functions as other timers. this manual uses x to describe two or more control bits (or addresses) in a bit name (or an expression). therefore, x should be substituted with 0 to 5 in this example to obtain the actual bit names and addresses. timer 0 : prun0 (d0/0x300786) ? 0x300786 + 8 0 = 0x300786 timer 1 : prun1 (d0/0x30078e) ? 0x300786 + 8 1 = 0x30078e timer 2 : prun2 (d0/0x300796) ? 0x300786 + 8 2 = 0x300796 timer 3 : prun3 (d0/0x30079e) ? 0x300786 + 8 3 = 0x30079e timer 4 : prun4 (d0/0x3007a6) ? 0x300786 + 8 4 = 0x3007a6 timer 5 : prun5 (d0/0x3007ae) ? 0x300786 + 8 5 = 0x3007ae x is used for not only timer numbers, but also memory block numbers, a/d converter channel numbers and others.
contents ii epson s1c33e08 technical manual contents i s1c33e08 specification s i.1 overview ..................................................................................................................... i-1- 1 i.2 block diagram ........................................................................................................... i-2- 1 i.3 pin d escription .......................................................................................................... i-3- 1 i.3.1 pin arrangement .......................................................................................................... i-3- 1 i.3.1.1 qfp package pin arrangement (s1c33e08f00a) ....................................... i-3- 1 i.3.1.2 pfbga package pin arrangement (s1c33e08b00a) .................................. i-3- 2 i.3.2 pin functions ............................................................................................................... i-3- 3 i.3.3 switching over the multiplexed pin functions ............................................................. i-3- 9 i.3.3.1 pin function select bits ................................................................................. i-3- 9 i.3.3.2 list of port function select registers ........................................................... i-3-1 2 0x3003a0 : p00Cp03 port function select register (pp0_03_cfp) ....................................... i-3-1 3 0x3003a1 : p04Cp07 port function select register (pp0_47_cfp) ....................................... i-3-1 4 0x3003a2 : p10Cp13 port function select register (pp1_03_cfp) ....................................... i-3-1 5 0x3003a3 : p14Cp17 port function select register (pp1_47_cfp) ....................................... i-3-1 6 0x3003a4 : p20Cp23 port function select register (pp2_03_cfp) ....................................... i-3-1 7 0x3003a5 : p24Cp27 port function select register (pp2_47_cfp) ....................................... i-3-1 8 0x3003a6 : p30Cp33 port function select register (pp3_03_cfp) ....................................... i-3-1 9 0x3003a7 : p34Cp36 port function select register (pp3_46_cfp) ....................................... i-3-2 0 0x3003a8 : p40Cp43 port function select register (pp4_03_cfp) ....................................... i-3-2 1 0x3003a9 : p44Cp47 port function select register (pp4_47_cfp) ....................................... i-3-2 2 0x3003 aa: p50Cp53 port function select register (pp5_03_cfp) ....................................... i-3-2 3 0x3003 ab: p54Cp57 port function select register (pp5_47_cfp) ....................................... i-3-2 4 0x3003 ac: p60Cp63 port function select register (pp6_03_cfp) ...................................... i-3-2 5 0x3003 ad: p64Cp67 port function select register (pp6_47_cfp) ...................................... i-3-2 6 0x3003 ae: p70Cp73 port function select register (pp7_03_cfp) ....................................... i-3-2 7 0x3003 af: p74 port function select register (pp7_4_cfp) ................................................. i-3-2 8 0x3003b0 : p80Cp83 port function select register (pp8_03_cfp) ....................................... i-3-2 9 0x3003b1 : p84Cp85 port function select register (pp8_45_cfp) ....................................... i-3-3 0 0x3003b2 : p90Cp93 port function select register (pp9_03_cfp) ....................................... i-3-3 1 0x3003b3 : p94Cp97 port function select register (pp9_47_cfp) ....................................... i-3-3 2 0x300c20 : pa0 Cpa3 port function select register (ppa_03_cfp) ....................................... i-3-3 3 0x300c21 : pa4 port function select register (ppa_4_cfp) ................................................. i-3-3 4 0x300c22 : pb0Cpb3 port function select register (ppb_03_cfp) ...................................... i-3-3 5 0x300c24 : pc0Cpc3 port function select register (ppc_03_cfp) ..................................... i-3-3 6 0x300c25 : pc4Cpc7 port function select register (ppc_47_cfp) ..................................... i-3-3 7 i.3.4 input/output cells and input/output characteristics ................................................... i-3-3 8 i.3.5 package ...................................................................................................................... i-3-4 1 i.3.5.1 qfp24-144 pin package ................................................................................ i-3-4 1 i.3.5.2 pfbga-180 pin package ............................................................................... i-3-4 3 i.3.5.3 thermal resistance of the package ............................................................. i-3-4 5 i.3.6 pad layout .................................................................................................................. i-3-4 6 i.4 power supply ............................................................................................................. i-4- 1 i.4.1 power supply pins ....................................................................................................... i-4- 1 i.4.2 operating voltage (v dd , v ss ) ........................................................................................ i-4- 2 i.4.3 power supply for pll (plv dd , plv ss ) .......................................................................... i-4- 2 i.4.4 power supply for i/o interface (v ddh ) .......................................................................... i-4- 2 i.4.5 power supply for analog circuits (av dd ) ..................................................................... i-4- 2 i.4.6 precautions on power supply ...................................................................................... i-4- 3
contents s1c33e08 technical manual epson iii i.5 cpu core and bus architecture .............................................................................. i-5- 1 i.5.1 features of the c33 pe core ....................................................................................... i-5- 1 i.5.2 cpu registers ............................................................................................................. i-5- 2 i.5.3 instruction set .............................................................................................................. i-5- 3 i.5. 4 trap table ..................................................................................................................... i-5- 7 i.5. 5 power-down mode ....................................................................................................... i-5- 9 i.5.6 debug mode ................................................................................................................ i-5-1 0 i.5.7 bus architecture .......................................................................................................... i-5-1 1 i.5.7.1 32-bit high-speed bus .................................................................................. i-5-1 1 i.5.7.2 sapb bus ..................................................................................................... i-5-1 2 i.5.7.3 external bus ................................................................................................ i-5-1 2 i.5. 8 chip id ........................................................................................................................ i-5-1 3 i.6 memory map .............................................................................................................. i-6- 1 i.6.1 boot address and gate rom ..................................................................................... i-6- 3 i.6.2 area 0 (a0ram) ........................................................................................................... i-6- 3 i.6.3 area 1 (specific rom for firmware) ........................................................................... i-6- 4 i.6.4 area 2 (debug area) ................................................................................................... i-6- 4 i.6.5 area 3 (ivram) ............................................................................................................ i-6- 4 i.6.6 area 3 (dst ram) ....................................................................................................... i-6- 4 i.6.7 area 6 (i/o area) .......................................................................................................... i-6- 5 i.6.8 external memory areas .............................................................................................. i-6- 5 i.7 electrical characteristics .......................................................................................... i-7- 1 i.7.1 absolute maximum rating ........................................................................................... i-7- 1 i.7.2 recommended operating conditions .......................................................................... i-7- 1 i.7.3 dc characteristics ....................................................................................................... i-7- 2 i.7.4 current consumption ................................................................................................... i-7- 3 i.7.5 a/d converter characteristics ...................................................................................... i-7- 5 i.7.6 oscillation characteristics ............................................................................................ i-7- 6 i.7.7 pll characteristics ...................................................................................................... i-7- 7 i.7.8 ac characteristics ....................................................................................................... i-7- 8 i.7.8.1 symbol description ........................................................................................ i-7- 8 i.7.8.2 ac characteristics measurement condition .................................................. i-7- 8 i.7.8.3 sramc ac characteristic tables .................................................................. i-7- 9 i.7.8.4 sramc ac characteristic timing charts ..................................................... i-7-1 0 i.7.8.5 sdram interface ac characteristics ........................................................... i-7-1 1 i.7.8.6 lcdc ac characteristics ............................................................................. i-7-1 4 i.7.9 usb dc and ac characteristics ................................................................................. i-7-2 7 i.8 basic external wiring diagram ................................................................................ i-8- 1 i.9 precautions on mounting ......................................................................................... i-9- 1
contents iv epson s1c33e08 technical manual ii bus m odule s ii.1 high-speed dma (hsdma) ..................................................................................... ii-1- 1 ii.1.1 functional outline of hsdma ..................................................................................... ii-1- 1 ii.1.2 i/o pins of hsdma ..................................................................................................... ii-1- 5 ii.1.3 programming control information ............................................................................... ii-1- 6 ii.1.3.1 standard mode and advanced mode ........................................................... ii-1- 6 ii.1.3.2 sequential access time for idma and hsdma ........................................... ii-1- 7 ii.1.3.3 setting the registers in dual-address mode ................................................ ii-1- 8 ii.1.3.4 setting the registers in single-address mode ............................................ ii-1-1 1 ii.1.4 enabling/disabling dma transfer ............................................................................... ii-1-1 4 ii.1.5 trigger source ............................................................................................................ ii-1-1 5 ii.1.6 operation of hsdma ................................................................................................. ii-1-1 6 ii.1.6.1 operation in dual-address mode ................................................................ ii-1-1 6 ii.1.6.2 operation in single-address mode .............................................................. ii-1-2 0 ii.1.7 interrupt function of hsdma ..................................................................................... ii-1-2 4 ii.1.8 hsdma operating clock ............................................................................................ ii-1-2 5 ii.1.9 details of control registers ....................................................................................... ii-1-2 6 0x301120C0x301150 : hsdma ch. x transfer counter registers (phs x _cnt) ...................... ii-1-2 8 0x301122C0x301152 : hsdma ch. x control registers ........................................................... ii-1-2 9 0x301124C0x301154: hsdma ch. x low-order source address setup registers (phs x _sadr) ................................................................................. ii-1-3 0 0x301126C0x301156 : hsdma ch. x high-order source address setup registers ................ ii-1-3 1 0x301128C0x301158 : hsdma ch. x low-order destination address setup registers (phs x _dadr) ................................................................................. ii-1-3 3 0x30112aC0x30115 a: hsdma ch. x high-order destination address setup registers ........ ii-1-3 4 0x30112cC0x30115 c: hsdma ch. x enable registers (phs x _en) ....................................... ii-1-3 6 0x30112eC0x30115 e: hsdma ch. x trigger flag registers (phs x _tf) ................................ ii-1-3 7 0x301162C0x301192 : hsdma ch. x control registers (phs x _advmode) for adv mode .... ii-1-3 8 0x301164C0x301196 : hsdma ch. x source address setup registers (phs x _ad_sadr) for adv mode ................................................... ii-1-4 0 0x301168C0x30119 a: hsdma ch. x destination address setup registers (phs x _adv_dadr) for adv mode ................................................. ii-1-4 2 0x30119 c: hsdma std/adv mode select register (phs_cntlmode) ............................. ii-1-4 4 0x30119 e: dma sequential access time register (phs_acctime) .................................... ii-1-4 5 ii.1.10 precautions .............................................................................................................. ii-1-4 6 ii.2 intelligent dma (idma) ............................................................................................ ii-2- 1 ii.2.1 functional outline of idma ......................................................................................... ii-2- 1 ii.2.2 programming control information ............................................................................... ii-2- 3 ii.2.2.1 setting the base address ............................................................................. ii-2- 3 ii.2.2.2 control information ....................................................................................... ii-2- 3 ii.2.3 idma invocation .......................................................................................................... ii-2- 8 ii.2.4 operation of idma ..................................................................................................... ii-2-1 1 ii.2.4.1 single transfer mode ................................................................................... ii-2-1 1 ii.2.4.2 successive transfer mode ........................................................................... ii-2-1 2 ii.2.4.3 block transfer mode .................................................................................... ii-2-1 3 ii.2.4.4 cause-of-interrupt processing by trigger type ............................................ ii-2-1 4 ii.2.5 linking ........................................................................................................................ ii-2-1 5 ii.2.6 interrupt function of intelligent dma .......................................................................... ii-2-1 6 ii.2.7 details of control registers ....................................................................................... ii-2-1 7 0x301100 : idma base address register 0 (pidmabase) ..................................................... ii-2-1 8 0x301102 : idma base address register 1 ............................................................................. ii-2-1 8
contents s1c33e08 technical manual epson v 0x301104 : idma start register (pidma_start) ................................................................... ii-2-1 9 0x301105 : idma enable register (pidma_en) ...................................................................... ii-2-2 0 ii.2.8 precautions ................................................................................................................ ii-2-2 1 ii.3 sram controller (sramc) ..................................................................................... ii-3- 1 ii.3.1 overview of the sramc ............................................................................................. ii-3- 1 ii.3.2 sramc pins ............................................................................................................... ii-3- 2 ii.3.3 external memory area (areas 4, 5, 7 to 22) ............................................................... ii-3- 3 ii.3.3.1 chip enable signals ...................................................................................... ii-3- 4 ii.3.3.2 area condition settings ................................................................................ ii-3- 4 ii.3.4 connection of external devices and bus operation ................................................... ii-3- 7 ii.3.4.1 connecting external devices ....................................................................... ii-3- 7 ii.3.4.2 data configuration in memory ...................................................................... ii-3- 7 ii.3.4.3 external bus operation ................................................................................. ii-3- 8 ii.3.5 sramc operating clock and bus clock .................................................................... ii-3- 9 ii.3.5.1 operating clock of the sramc .................................................................... ii-3- 9 ii.3.5.2 generation of the bus clock ........................................................................ ii-3-1 0 ii.3.5.3 external output of the bus clock ................................................................. ii-3-1 0 ii.3.6 bus access timing chart ........................................................................................... ii-3-1 1 ii.3.6.1 sram read/write timings with no external #wait ................................... ii-3-1 1 ii.3.6.2 sram read/write timings with external #wait ......................................... ii-3-1 3 ii.3.6.3 sram read/write timings with #ce4/#ce11 setup time ......................... ii-3-1 4 ii.3.6.4 sram read timings with #ce9 output disable time ................................. ii-3-1 5 ii.3.7 control register details ............................................................................................. ii-3-1 6 0 x 301500 : bclk and setup time control register (psramc_bclk_setup ) ......................... ii-3-1 7 0x301504 : wait control register (psramc_swait) ............................................................. ii-3-1 8 0x301508 : device size setup register (psramc_slv_size) .............................................. ii-3-2 0 0x30150 c: device type set up register (psramc_a0_bsl ) ................................................. ii-3-2 1 0x301510 : area location set up register (psramc_ als ) ..................................................... ii-3-2 2 ii.3.8 precautions ................................................................................................................ ii-3-2 3 ii.4 sdram controller (sdramc) ................................................................................ ii-4- 1 ii.4.1 sd ram interface ........................................................................................................ ii-4- 1 ii.4.1.1 overview of the sdram interface ................................................................ ii-4- 1 ii.4.1.2 sdramc pins .............................................................................................. ii-4- 2 ii.4.1.3 configuration of sdram .............................................................................. ii-4- 3 ii.4.1.4 sdramc operating clock and sdram clock ............................................. ii-4- 8 ii.4.1.5 control and operation of sdram interface ................................................. ii-4-1 0 ii.4.2 instruction/data queue buffers .................................................................................. ii-4-1 8 ii.4.2.1 overview ...................................................................................................... ii-4-1 8 ii.4.2.2 iqb (instruction queue buffer) .................................................................... ii-4-1 8 ii.4.2.3 dqb (data queue buffer) ............................................................................ ii-4-1 9 ii.4.2.4 operations using iqb/dqb .......................................................................... ii-4-2 0 ii.4.3 bus arbiter ................................................................................................................. ii-4-2 1 ii.4.3.1 overview ...................................................................................................... ii-4-2 1 ii.4.3.2 controlling the bus arbiter ........................................................................... ii-4-2 1 ii.4.4 control register details ............................................................................................. ii-4-2 2 0x301600 : sdram initial register (psdramc_ini) .............................................................. ii-4-2 3 0x301604 : sdram configuration register (psdramc_ctl) ............................................... ii-4-2 5 0x301608 : sdram refresh register (psdramc_ref) ........................................................ ii-4-2 7 0x301610 : sdram application configuration register (psdramc_app) ............................ ii-4-2 9 ii.4.5 precautions ................................................................................................................ ii-4-3 1
contents vi epson s1c33e08 technical manual iii p eripheral modules 1 (system ) iii.1 clock management unit (cmu) ............................................................................. iii-1- 1 iii.1.1 overview of the cmu ................................................................................................ iii-1- 1 iii.1.2 reset input and initial reset ..................................................................................... iii-1- 2 iii.1.2.1 initial reset pin ........................................................................................... iii-1- 2 iii.1.2.2 initial reset status ..................................................................................... iii-1- 2 iii.1.2.3 power-on reset .......................................................................................... iii-1- 3 iii.1.2.4 precautions to be taken during initial reset ............................................... iii-1- 4 iii.1.3 nmi input .................................................................................................................. iii-1- 5 iii.1.4 selecting the system clock source .......................................................................... iii-1- 6 iii.1.5 controlling the oscillator circuit ................................................................................ iii-1- 7 iii.1.5.1 osc3 oscillator circuit ............................................................................... iii-1- 7 iii.1.5.2 setting the osc3 divider ............................................................................ iii-1- 8 iii.1.5.3 osc1 oscillator circuit ............................................................................... iii-1- 8 iii.1.6 controlling the pll ................................................................................................... iii-1-1 0 iii.1.6.1 on/off control of the pll .......................................................................... iii-1-1 0 iii.1.6.2 selecting the pll input clock ................................................................... iii-1-1 0 iii.1.6.3 setting the frequency multiplication rate ................................................. iii-1-1 1 iii.1.6.4 other pll settings .................................................................................... iii-1-1 2 iii.1.6.5 power supply for pll ................................................................................ iii-1-1 3 iii.1.7 control of the sscg ................................................................................................ iii-1-1 4 iii.1.7.1 turning the sscg on/off .......................................................................... iii-1-1 4 iii.1.7.2 setting ss modulation parameters ............................................................ iii-1-1 5 iii.1.8 setting the main system clock (mclk) ................................................................... iii-1-1 6 iii.1.9 controlling clock supply .......................................................................................... iii-1-1 7 iii.1.9.1 mclk clock supply to each module ......................................................... iii-1-1 7 iii.1.9.2 automatic clock control in halt mode ..................................................... iii-1-1 7 iii.1.9.3 clock supply to the lcdc ........................................................................ iii-1-1 8 iii.1.9.4 clock supply to the sdramc .................................................................. iii-1-1 9 iii.1.9.5 clock supply to the sramc ...................................................................... iii-1-1 9 iii.1.9.6 clock supply to the gpio .......................................................................... iii-1-2 0 iii.1.9.7 clock supply to the efsio ....................................................................... iii-1-2 0 iii.1.9.8 clock supply to the usb ........................................................................... iii-1-2 0 iii.1.9.9 clock supply to the rtc ........................................................................... iii-1-2 1 iii.1.10 setting the external clock output (cmu_clk) ..................................................... iii-1-2 2 iii.1.11 standby modes ...................................................................................................... iii-1-2 3 iii.1.11.1 halt mode .............................................................................................. iii-1-2 3 iii.1.11.2 sleep mode ........................................................................................... iii-1-2 3 iii.1.11.3 precautions .............................................................................................. iii-1-2 5 iii.1.12 clock setup procedure .......................................................................................... iii-1-2 6 iii.1.12.1 changing the clock source from osc3 to pll ....................................... iii-1-2 6 iii.1.12.2 changing the clock source from pll to osc3, then turning off the pll ..................................................................... iii-1-2 7 iii.1.12.3 changing the clock source from osc3 or pll to osc1, then turning off osc3 and pll ......................................................... iii-1-2 8 iii.1.12.4 changing the clock source from osc1 to osc3 ................................... iii-1-2 9 iii.1.12.5 changing the clock source from osc1 to pll ....................................... iii-1-3 0 iii.1.12.6 turning off osc3 during sleep ............................................................ iii-1-3 1 iii.1.12.7 sleep keeping oscillation on (without clock change) ......................... iii-1-3 2 iii.1.13 power-down control .............................................................................................. iii-1-3 3
contents s1c33e08 technical manual epson vii iii.1.14 details of control registers ................................................................................... iii-1-3 4 0x301b00 : gated clock control register 0 (pcmu_gatedclk0) ....................................... iii-1-3 5 0x301b04 : gated clock control register 1 (pcmu_gatedclk1) ....................................... iii-1-3 7 0x301b08 : system clock control register (pcmu_clkcntl) ............................................. iii-1-4 0 0x301b0 c: pll control register (pcmu_pll) ..................................................................... iii-1-4 4 0x301b10 : sscg macro control register (pcmu_sscg) ................................................... iii-1-4 6 0x301b14 : clock option register (pcmu_opt) .................................................................... iii-1-4 7 0x301b24 : clock control protect register (pcmu_protect) ............................................. iii-1-4 9 iii.1.15 precautions ............................................................................................................ iii-1-5 0 iii.2 interrupt controller (itc) ....................................................................................... iii-2- 1 iii.2.1 outline of interrupt functions .................................................................................... iii-2- 1 iii.2.1.1 maskable interrupts .................................................................................... iii-2- 1 iii.2.1.2 causes of interrupt and intelligent dma ..................................................... iii-2- 4 iii.2.1.3 nonmaskable interrupt (nmi) ..................................................................... iii-2- 4 iii.2.1.4 interrupt processing by the cpu ................................................................ iii-2- 4 iii.2.1.5 clearing standby mode by interrupts ......................................................... iii-2- 4 iii.2.2 trap table .................................................................................................................. iii-2- 6 iii.2.3 itc operating clock .................................................................................................. iii-2- 7 iii.2.4 control of maskable interrupts .................................................................................. iii-2- 8 iii.2.4.1 structure of the interrupt controller ............................................................ iii-2- 8 iii.2.4.2 processor status register (psr) ............................................................... iii-2- 8 iii.2.4.3 cause-of-interrupt flag and interrupt enable register ............................... iii-2- 9 iii.2.4.4 interrupt priority register and interrupt levels .......................................... iii-2-1 0 iii.2.5 idma invocation ....................................................................................................... iii-2-1 1 iii.2.6 hsdma invocation ................................................................................................... iii-2-1 3 iii.2.7 details of control registers ..................................................................................... iii-2-1 4 0x300260 : port input 0C1 interrupt priority register (pint_pp01l) ...................................... iii-2-1 6 0x300261 : port input 2C3 interrupt priority register (pint_pp23l) ...................................... iii-2-1 7 0x300262 : key input interrupt priority register (pint_pk01l) .............................................. iii-2-1 8 0x300263 : hsdma ch.0C1 interrupt priority register (pint_phsd01l) .............................. iii-2-1 9 0x300264 : hsdma ch.2C3 interrupt priority register (pint_phsd23l) .............................. iii-2-2 0 0x300265 : idma interrupt priority register (pint_pdm) ....................................................... iii-2-2 1 0x300266 : 16 -bit timer 0C1 interrupt priority register (pint_p16t01) ................................. iii-2-2 2 0x300267 : 16 -bit timer 2C3 interrupt priority register (pint_p16t23) ................................. iii-2-2 3 0x300268 : 16 -bit timer 4C5 interrupt priority register (pint_p16t45) ................................. iii-2-2 4 0x300269 : lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_psi00) ............. iii-2-2 5 0x30026 a: serial i/f ch.1 , a/d interrupt priority register (pint_psi01 _pad) ..................... iii-2-2 6 0x30026 b: rtc interrupt priority register (pint_prtc) ...................................................... iii-2-2 7 0x30026 c: port input 4C5 interrupt priority register (pint_pp45l) ...................................... iii-2-2 8 0x30026 d: port input 6C7 interrupt priority register (pint_pp67l) ...................................... iii-2-2 9 0x30026 e: serial i/f ch.2 , spi interrupt priority register (pint_psi02_pspi) .................... iii-2-3 0 0x300270 : key input, port input 0C3 interrupt enable register (pint_ek01_ep03) ............. iii-2-3 1 0x300271 : dma interrupt enable register (pint_edma) ..................................................... iii-2-3 2 0x300272 : 16 -bit timer 0C1 interrupt enable register (pint_e16t01) ................................. iii-2-3 3 0x300273 : 16 -bit timer 2C3 interrupt enable register (pint_e16t23) ................................. iii-2-3 4 0x300274 : 16 -bit timer 4C5 interrupt enable register (pint_e16t45) ................................. iii-2-3 5 0x300276 : serial i/f ch.0C1 interrupt enable register (pint_esif01) ................................. iii-2-3 6 0x300277 : port input 4C7 , rtc, a/d interrupt enable register (pint_ep47 _ertc_ead) .. iii-2-3 7 0x300278 : lcdc interrupt enable register (pint_elcdc) .................................................. iii-2-3 8 0x300279 : serial i/f ch.2 , spi interrupt enable register (pint_esif2_espi) ..................... iii-2-3 9 0x300280 : key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) ...... iii-2-4 0 0x300281 : dma interrupt cause flag register (pint_fdma) .............................................. iii-2-4 2 0x300282 : 16 -bit timer 0C1 interrupt cause flag register (pint_f16t01) .......................... iii-2-4 3 0x300283 : 16 -bit timer 2C3 interrupt cause flag register (pint_f16t23) .......................... iii-2-4 4
contents viii epson s1c33e08 technical manual 0x300284 : 16 -bit timer 4C5 interrupt cause flag register (pint_f16t45) .......................... iii-2-4 5 0x300286 : serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) .......................... iii-2-4 6 0x300287 : port input 4C7 , rtc, a/d interrupt cause flag register (pint_fp47 _frtc_fad) ................................................................................ iii-2-4 7 0x300288 : lcdc interrupt cause flag register (pint_flcdc) ........................................... iii-2-4 8 0x300289 : serial i/f ch.2 , spi interrupt cause flag register (pint_fsif2_fspi) .............. iii-2-4 9 0x300290 : port input 0C3, hsdma ch.0C1, 16 -bit timer 0 idma request register (pidmareq_rp03_rhs_r16t0) .................................................................. iii-2-5 0 0x300291 : 16 -bit timer 1C4 idma request register (pidmareq_r16t14) ........................ iii-2-5 1 0x300292 : 16 -bit timer 5 , serial i/f ch.0 idma request register (pidmareq_r16t5_rsif0) ........................................................................... iii-2-5 2 0x300293 : serial i/f ch.1 , a/d, port input 4C7 idma request register (pidmareq_rsif1_rad_rp47) ................................................................... iii-2-5 3 0x300294 : port input 0C3, hsdma ch.0C1, 16 -bit timer 0 idma enable register (pidmaen_dep03_dehs_de16t0) .............................................................. iii-2-5 4 0x300295 : 16 -bit timer 1C4 idma enable register (pidmaen_de16t14) ........................... iii-2-5 5 0x300296 : 16 -bit timer 5 , serial i/f ch.0 idma enable register (pidmaen_de16t5_desif0) ......................................................................... iii-2-5 6 0x300297 : serial i/f ch.1 , a/d, port input 4C7 idma enable register (pidmaen_desif1_dead_dep47) ............................................................... iii-2-5 7 0x300298 : hsdma ch.0C1 trigger set-up register (phsdma_htgr1) .............................. iii-2-5 8 0x300299 : hsdma ch.2C3 trigger set-up register (phsdma_htgr2) .............................. iii-2-5 8 0x30029 a: hsdma software trigger register (phsdma_hsofttgr) ............................... iii-2-6 0 0x30029 b: lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc_rsif2_rspi) ............................................................... iii-2-6 1 0x30029 c: lcdc, serial i/f ch.2 , spi idma enable register (pidmaen_delcdc_desif2_despi) .......................................................... iii-2-6 2 0x30029 f: flag set/reset method select register (prst_reset) ..................................... iii-2-6 3 0x3002a0 : port input 8C9 interrupt priority register (pint_pp89l) ...................................... iii-2-6 4 0x3002a1 : port input 10C11 interrupt priority register (pint_pp1011l) .............................. iii-2-6 5 0x3002a2 : port input 12C13 interrupt priority register (pint_pp1213l) .............................. iii-2-6 6 0x3002a3 : port input 14C15 interrupt priority register (pint_pp1415l) .............................. iii-2-6 7 0x3002a4 : i 2 s interrupt priority register (pint_pi 2s) ........................................................... iii-2-6 8 0x3002a6 : port input 8C15 interrupt enable register (pint_ep815) .................................... iii-2-6 9 0x3002a7 : i 2 s interrupt enable register (pint_ei 2s) ........................................................... iii-2-7 0 0x3002a9 : port input 8C15 interrupt cause flag register (pint_fp815) ............................. iii-2-7 1 0x3002 aa: i 2 s interrupt cause flag register (pint_fi 2s) ................................................... iii-2-7 2 0x3002 ac: port input 8C15 idma request register (pidmareq_rp815) .......................... iii-2-7 3 0x3002 ad: i 2 s idma request register (pidmareq_ri2s) ................................................. iii-2-7 4 0x3002 ae: port input 8C15 idma enable register (pidmaen_dep815) ............................. iii-2-7 5 0x3002 af: i 2 s idma enable register (pidmaen_dei 2s) .................................................... iii-2-7 6 0x3003c4 : port input interrupt select register 3 (ppintsel_spt811) ............................... iii-2-7 7 iii.2.8 precautions .............................................................................................................. iii-2-7 8 iii.3 real-time clock (rtc) ........................................................................................... iii-3- 1 iii.3.1 overview of the rtc ................................................................................................. iii-3- 1 iii.3.2 rtc counters ........................................................................................................... iii-3- 2 iii.3.3 control of the rtc .................................................................................................... iii-3- 5 iii.3.3.1 controlling the operating clock .................................................................. iii-3- 5 iii.3.3.2 initial sequence of the rtc ........................................................................ iii-3- 6 iii.3.3.3 selecting 12/24-hour mode and setting the counters ................................ iii-3- 7 iii.3.3.4 starting, stopping, and resetting counters ............................................... iii-3- 7 iii.3.3.5 counter hold and busy flag ....................................................................... iii-3- 8 iii.3.3.6 reading from and writing to counters in operation ................................... iii-3- 9 iii.3.3.7 30-second correction ................................................................................. iii-3- 9 iii.3.4 rtc interrupts .......................................................................................................... iii-3-1 0
contents s1c33e08 technical manual epson ix iii.3.5 osc1 oscillator circuit ............................................................................................ iii-3-1 1 iii.3.5.1 input/output pins of the osc1 oscillator circuit ....................................... iii-3-1 1 iii.3.5.2 structure of the osc1 oscillator circuit .................................................... iii-3-1 1 iii.3.5.3 oscillation control ..................................................................................... iii-3-1 2 iii.3.6 details of control registers ..................................................................................... iii-3-1 3 0x301900 : rtc interrupt status register (prtcintstat) .................................................... iii-3-1 4 0x301904 : rtc interrupt mode register (prtcintmode) .................................................. iii-3-1 5 0x301908 : rtc control register (prtc_cntl0) ................................................................. iii-3-1 6 0x30190 c: rtc access control register (prtc_cntl1) .................................................... iii-3-1 8 0x301910 : rtc second register (prtcsec) ....................................................................... iii-3-1 9 0x301914 : rtc minute register (prtcmin) ......................................................................... iii-3-2 0 0x301918 : rtc hour register (prtchour) ........................................................................ iii-3-2 1 0x30191 c: rtc day register (prtcday) ............................................................................. iii-3-2 2 0x301920 : rtc month register (prtcmonth) ................................................................... iii-3-2 3 0x301924 : rtc year register (prtcyear) .......................................................................... iii-3-2 4 0x301928 : rtc days of week register (prtcdayweek) ................................................... iii-3-2 5 iii.3.7 precautions .............................................................................................................. iii-3-2 6 iii.4 misc registers ........................................................................................................ iii-4- 1 iii.4.1 rtc and usb wait control registers ....................................................................... iii-4- 1 iii.4.1.1 setting wait cycles for accessing the rtc ................................................ iii-4- 1 iii.4.1.2 settings for the usb ................................................................................... iii-4- 1 iii.4.2 debug port mux register ......................................................................................... iii-4- 2 iii.4.3 boot register ............................................................................................................ iii-4- 3 iii.4.4 pin control registers ................................................................................................ iii-4- 4 iii.4.4.1 pull-up control ............................................................................................ iii-4- 4 iii.4.4.2 driving bus signals low ............................................................................. iii-4- 4 iii.4.5 misc register operating clock .................................................................................. iii-4- 5 iii.4.6 details of control registers ...................................................................................... iii-4- 6 0x300010 : rtc wait control register (pmisc_rtcwt) ....................................................... iii-4- 7 0x300012 : usb wait control register (pmisc_usbwt) ....................................................... iii-4- 8 0x300014 : debug port mux register (pmisc_pmux) ........................................................... iii-4- 9 0x300016 : performance analyzer control register (pmisc_pac) ........................................ iii-4-1 0 0x300018 : boot register (pmisc_boot) .............................................................................. iii-4-1 1 0x30001 a: corom switch register (pmisc_corom) ........................................................ iii-4-1 2 0x300020 : misc protect register (pmisc_prot) ................................................................. iii-4-1 3 0x300c41 : bus signal low drive control register (pmisc_buslow) ................................ iii-4-1 4 0x300c42 : p0 pull-up control register (pmisc_pup0) ........................................................ iii-4-1 5 0x300c43 : p1 pull-up control register (pmisc_pup1) ........................................................ iii-4-1 6 0x300c44 : p2 pull-up control register (pmisc_pup2) ........................................................ iii-4-1 7 0x300c45 : p3 pull-up control register (pmisc_pup3) ........................................................ iii-4-1 8 0x300c46 : p4 pull-up control register (pmisc_pup4) ........................................................ iii-4-1 9 0x300c47 : p5 pull-up control register (pmisc_pup5) ........................................................ iii-4-2 0 0x300c48 : p6 pull-up control register (pmisc_pup6) ........................................................ iii-4-2 1 0x300c49 : p7 pull-up control register (pmisc_pup7) ........................................................ iii-4-2 2 0x300c4 a: p8 pull-up control register (pmisc_pup8) ....................................................... iii-4-2 3 0x300c4 b: p9 pull-up control register (pmisc_pup9) ....................................................... iii-4-2 4 0x300c4 c: pa pull-up control register (pmisc_pupa) ....................................................... iii-4-2 5 0x300c4 d: pb pull-up control register (pmisc_pupb) ...................................................... iii-4-2 6 iii.4.7 precautions .............................................................................................................. iii-4-2 7
contents x epson s1c33e08 technical manual iv peripheral m odules 2 (t imers ) iv. 1 16 -bit timers (t16) ................................................................................................. iv- 1- 1 iv. 1.1 configuration of 16 -bit timer ..................................................................................... iv- 1- 1 iv. 1.2 i/o pins of 16 -bit timers ............................................................................................ iv- 1- 3 iv. 1.3 uses of 16 -bit timers ................................................................................................ iv- 1- 4 iv. 1.4 16 -bit timer operating clock ..................................................................................... iv- 1- 5 iv. 1.5 control and operation of 16 -bit timer ....................................................................... iv- 1- 6 iv. 1.6 controlling clock output .......................................................................................... iv- 1-1 0 iv. 1.7 16 -bit timer interrupts and dma .............................................................................. iv- 1-1 3 iv. 1.8 details of control registers ..................................................................................... iv- 1-1 6 0x300780C0x3007a8 : 16 -bit timer x comparison data a setup registers (pt16_cr x a) .... iv- 1-1 7 0x300782C0x3007 aa: 16 -bit timer x comparison data b setup registers (pt16_cr x b) ... iv- 1-1 8 0x300784C0x3007 ac: 16 -bit timer x counter data registers (pt16_tc x ) ........................... iv- 1-1 9 0x300786C0x3007 ae: 16 -bit timer x control registers (pt16_ctl x ) .................................. iv- 1-2 0 0x3007d0C0x3007d4 : da16 ch. x registers (pda16_cr x a) ................................................ iv- 1-2 2 0x3007 dc: count pause register (pt16 _cnt_pause) ....................................................... iv- 1-2 3 0x3007 de: 16 -bit timer std/adv mode select register (pt16 _advmode) ....................... iv- 1-2 4 0x3007e0C0x3007ea: 16 -bit time r x clock control registers (pt16_clkctl _ x ) ............... iv- 1-2 5 iv. 1.9 precautions .............................................................................................................. iv- 1-2 6 iv. 2 watchdog timer (wdt) .......................................................................................... iv- 2- 1 iv. 2.1 configuration of the watchdog timer ....................................................................... iv- 2- 1 iv. 2.2 input/output pins of the watchdog timer ................................................................. iv- 2- 2 iv. 2.3 operating clock of the watchdog timer ................................................................... iv- 2- 3 iv. 2.4 control of the watchdog timer .................................................................................. iv- 2- 4 iv. 2.4.1 setting up the watchdog timer .................................................................. iv- 2- 4 iv. 2.4.2 starting/stopping the watchdog timer ...................................................... iv- 2- 5 iv. 2.4.3 resetting the watchdog timer ................................................................... iv- 2- 5 iv. 2.4.4 operation in standby mode ........................................................................ iv- 2- 5 iv. 2.4.5 clock output of the watchdog timer ......................................................... iv- 2- 6 iv. 2.4.6 external nmi output ................................................................................... iv- 2- 6 iv. 2.5 details of control registers ...................................................................................... iv- 2- 7 0x300660 : watchdog timer write-protect register (pwd_wp) ............................................. iv- 2- 8 0x300662 : watchdog timer enable register (pwd_en) ........................................................ iv- 2- 9 0x300664: watchdog timer comparison data setup register 0 (pwd_comp_low) ......... iv- 2-1 1 0x300666 : watchdog timer comparison data setup register 1 (pwd_comp_high) ........ iv- 2-1 1 0x300668 : watchdog timer count register 0 (pwd_cnt_low) ......................................... iv- 2-1 2 0x30066 a: watchdog timer count register 1 (pwd_cnt_high) ........................................ iv- 2-1 2 0x30066 c: watchdog timer control register (pwd_cntl) .................................................. iv- 2-1 3 iv. 2.6 precautions .............................................................................................................. iv- 2-1 4
contents s1c33e08 technical manual epson xi v peripheral m odules 3 ( i nterface ) v. 1 general-purpose serial interface ( efsio) ............................................................. v- 1- 1 v. 1.1 configuration of serial interfaces ................................................................................ v- 1- 1 v. 1.1.1 features of serial interfaces ......................................................................... v- 1- 1 v. 1.1.2 i/o pins of serial interface ............................................................................ v- 1- 2 v. 1.1.3 setting interface mode and transfer mode ................................................... v- 1- 3 v. 1.1.4 serial interface operating clock ................................................................... v- 1- 4 v. 1.1.5 standard mode and advanced mode ........................................................... v- 1- 5 v. 1.2 baud-rate timer (setting baud rate) ........................................................................ v- 1- 6 v. 1.3 clock-synchronized interface ..................................................................................... v- 1- 8 v. 1.3.1 outline of clock-synchronized interface ....................................................... v- 1- 8 v. 1.3.2 setting clock-synchronized interface ........................................................... v- 1- 9 v. 1.3.3 control and operation of clock-synchronized transfer ............................... v- 1-1 0 v. 1.4 asynchronous interface .............................................................................................. v- 1-1 7 v. 1.4.1 outline of asynchronous interface ............................................................... v- 1-1 7 v. 1.4.2 setting asynchronous interface ................................................................... v- 1-1 8 v. 1.4.3 control and operation of asynchronous transfer ........................................ v- 1-2 0 v. 1.5 irda interface ............................................................................................................. v- 1-2 5 v. 1.5.1 outline of irda interface ............................................................................... v- 1-2 5 v. 1.5.2 setting irda interface ................................................................................... v- 1-2 5 v. 1.5.3 control and operation of irda interface ....................................................... v- 1-2 7 v. 1.6 iso7816 interface (ch.1) ........................................................................................... v- 1-2 8 v. 1.6.1 outline of iso7816 interface ....................................................................... v- 1-2 8 v. 1.6.2 setting iso7816 interface ............................................................................ v- 1-2 9 v. 1.6.3 control and operation of iso7816 mode .................................................... v- 1-3 2 v. 1.7 serial interface interrupts and dma ........................................................................... v- 1-3 7 v. 1.8 details of control registers ....................................................................................... v- 1-4 0 0x300b00C0x300b20 : serial i/f ch. x transmit data registers ( pefsif x _txd) .................... v- 1-4 1 0x300b01C0x300b21 : serial i/f ch. x receive data registers ( pefsif x _rxd) .................... v- 1-4 2 0x300b02C0x300b22 : serial i/f ch. x status registers ( pefsif x _status) ......................... v- 1-4 3 0x300b03C0x300b23 : serial i/f ch. x control registers ( pefsif x _ctl) .............................. v- 1-4 5 0x300b04C0x300b24 : serial i/f ch. x irda registers ( pefsif x _irda) ................................. v- 1-4 7 0x300b05C0x300b25 : serial i/f ch. x baud-rate timer control registers ( pefsif x _brtrun) ....................................................................... v- 1-4 9 0x300b06C0x300b26 : serial i/f ch. x baud-rate timer reload data registers ( lsb) ( pefsif x _brtrdl) ........................................................................ v- 1-5 0 0x300b07 C0x300b27 : serial i/f ch. x baud-rate timer reload data registers ( msb) ( pefsif x _brtrdm) ....................................................................... v- 1-5 0 0x300b08 C0x300b28 : serial i/f ch. x baud-rate timer count data registers ( lsb) ( pefsif x _brtcdl) ........................................................................ v- 1-5 1 0x300b09 C0x300b29 : serial i/f ch. x baud-rate timer count data registers ( msb) ( pefsif x _brtcdm) ....................................................................... v- 1-5 1 0x300b1a : serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) ................ v- 1-5 2 0x300b 1 b : serial i/f ch.1 iso7816 mode status register (pefsif1_7816 sta) .................. v- 1-5 4 0x300b 1 c : serial i/f ch.1 iso7816 mode fi/di ratio register ( lsb) (pefsif1 _fidil) ...... v- 1-5 5 0x300b 1 d : serial i/f ch.1 iso7816 mode fi/di ratio register ( msb) (pefsif1 _fidim) .... v- 1-5 5 0x300b 1 e : serial i/f ch.1 transmit time guard register (pefsif1 _ttgr) ......................... v- 1-5 7 0x300b 1 f : serial i/f ch.1 iso7816 mode output clock setup register (pefsif1 _clknum) ....................................................................... v- 1-5 8 0x300b4 f: serial i/f std/adv mode select register ( pefsif_adv) ................................... v- 1-5 9 v. 1.9 precautions ................................................................................................................ v- 1-6 0
contents xii epson s1c33e08 technical manual v. 2 serial peripheral interface (spi) ............................................................................. v- 2- 1 v. 2.1 outline of spi module ................................................................................................. v- 2- 1 v. 2.2 i/o pins of spi module ................................................................................................ v- 2- 2 v. 2.3 spi operating clock .................................................................................................... v- 2- 3 v. 2.4 setting spi module ..................................................................................................... v- 2- 4 v. 2.5 control of data transfer .............................................................................................. v- 2- 6 v. 2.6 spi interrupts and dma ............................................................................................. v- 2-1 0 v. 2.7 details of control registers ....................................................................................... v- 2-1 3 0x301700 : spi receive data register (pspi_rxd) ............................................................... v- 2-1 4 0x301704 : spi transmit data register (pspi_txd) ............................................................... v- 2-1 5 0x301708 : spi control register 1 (pspi_ctl1) ..................................................................... v- 2-1 6 0x30170c: spi control register 2 (pspi_ctl2) .................................................................... v- 2-1 8 0x301710 : spi wait register (pspi_wait) ............................................................................. v- 2-1 9 0x301714 : spi status register (pspi_stat) .......................................................................... v- 2-2 0 0x301718 : spi interrupt control register (pspi_int) ............................................................. v- 2-2 1 0x30171 c: spi receive data mask register (pspi_rxmk) .................................................. v- 2-2 3 v. 2.8 precautions ................................................................................................................ v- 2-2 4 v. 3 direction control serial interface (dcsio) ............................................................ v- 3- 1 v. 3.1 outline of dcsio ........................................................................................................ v- 3- 1 v. 3.2 i/o pins of dcsio ....................................................................................................... v- 3- 2 v. 3.3 dcsio operating clock .............................................................................................. v- 3- 3 v. 3.4 setting dcsio module ................................................................................................ v- 3- 4 v. 3.5 control of data transfer .............................................................................................. v- 3- 7 v. 3.6 dcsio interrupts and dma ........................................................................................ v- 3-1 1 v. 3.7 details of control registers ....................................................................................... v- 3-1 3 0x301800 : dcsio control register (pdcsio_ctl) ............................................................... v- 3-1 4 0x301804 : dcsio data load register (pdcsio_load) ....................................................... v- 3-1 5 0x301808 : dcsio receive data register (pdcsio_rcv) .................................................... v- 3-1 6 0x301814 : dcsio interrupt control register (pdcsio_int) ................................................. v- 3-1 7 0x301818 : dcsio status register (pdcsio_stat) ............................................................... v- 3-1 8 0x30181 c: dcsio port direction control register (pdcsio_dir) ........................................ v- 3-1 9 v. 3.8 precautions ................................................................................................................ v- 3-2 0 v. 4 card interface (card) ............................................................................................. v- 4- 1 v. 4.1 outline of the card interface ....................................................................................... v- 4- 1 v .4.2 card interface pins ...................................................................................................... v- 4- 2 v. 4.3 card area .................................................................................................................... v- 4- 3 v. 4.3.1 selecting the area ........................................................................................ v- 4- 3 v. 4.3.2 setting area access conditions .................................................................... v- 4- 3 v. 4.4 card interface control signals .................................................................................... v- 4- 4 v. 4.4.1 smartmedia interface ................................................................................... v- 4- 4 v. 4.4.2 compactflash interface ................................................................................ v- 4- 5 v. 4.4.3 pc card interface ......................................................................................... v- 4- 5 v. 4.5 card interface operating clock ................................................................................... v- 4- 7 v. 4.6 ecc generator ........................................................................................................... v- 4- 8 v. 4.7 details of control registers ....................................................................................... v- 4-1 1 0x300300 : card i/f area configuration register (pcardsetup) ......................................... v- 4-1 2 0x300302 : card i/f output port configuration register (pcardfuncsel05) ..................... v- 4-1 3 0x300310 : ecc trigger area select register (pecctrigsel) ............................................. v- 4-1 4 0x300311 : ecc reset/ready register (peccrstrdy) ........................................................ v- 4-1 5 0x300312 : ecc enable register (peccena) ........................................................................ v- 4-1 6 0x300313 : ecc mode register (peccmd) ............................................................................ v- 4-1 7
contents s1c33e08 technical manual epson xiii 0x300314 : area 0 ecc column parity data register (pecc0cp) ......................................... v- 4-1 8 0x300316 : area 0 ecc line parity register 0 (pecc0lpl) ................................................... v- 4-1 9 0x300317 : area 0 ecc line parity register 1 (pecc0lph) .................................................. v- 4-1 9 0x300318 : area 1 ecc column parity data register (pecc1cp) ......................................... v- 4-2 0 0x30031 a: area 1 ecc line parity register 0 (pecc1lpl) ................................................... v- 4-2 1 0x30031 b: area 1 ecc line parity register 1 (pecc1lph) .................................................. v- 4-2 1 v. 4.8 precautions ................................................................................................................ v- 4-2 2 v. 5 i 2 s interface ( i 2 s ) ...................................................................................................... v- 5- 1 v. 5.1 outline of i 2 s module .................................................................................................. v- 5- 1 v. 5.2 output pins of i 2 s module ........................................................................................... v- 5- 2 v. 5.3 i 2 s module operating clock ........................................................................................ v- 5- 3 v. 5.4 setting i 2 s module ...................................................................................................... v- 5- 4 v. 5.5 data output control .................................................................................................... v- 5- 9 v. 5.6 i 2 s interrupt ................................................................................................................ v- 5-1 1 v. 5.7 details of control registers ....................................................................................... v- 5-1 2 0x301c00 : i 2 s control register (pi2 s_control) ................................................................ v- 5-1 3 0x301c04 : i 2 s mclk divide ratio register (pi2 s_dv_mclk) .............................................. v- 5-1 6 0x301c08 : i 2 s audio clock divide ratio register (pi 2 s_dv_lrclk) .................................... v- 5-1 7 0x301c0 c: i 2 s start register (pi2 s_start) .......................................................................... v- 5-1 8 0x301c10 : i 2 s hsdma mode select register (pi2s_hsdmamd) ......................................... v- 5-1 9 0x301c14 : i 2 s fifo status register (pi2s_fifo_empty) ................................................... v- 5-2 0 0x301c20 : i 2 s fifo register (pi2s_fifo) ............................................................................. v- 5-2 1
contents xiv epson s1c33e08 technical manual vi peripheral m odules 4 ( port s ) vi.1 general-purpose i/o ports (gpio) ....................................................................... vi-1- 1 vi.1.1 structure of i/o port .................................................................................................. vi-1- 1 vi.1.2 selecting the i/o pin functions ................................................................................ vi-1- 1 vi.1.3 i/o control register and i/o modes ......................................................................... vi-1- 2 vi.1.4 input interrupt ........................................................................................................... vi-1- 3 vi.1.4.1 port input interrupt ..................................................................................... vi-1- 3 vi.1.4.2 key input interrupt ...................................................................................... vi-1- 5 vi.1.4.3 control registers of the interrupt controller ............................................... vi-1- 7 vi.1.5 i/o port operating clock ........................................................................................... vi-1- 9 vi.1.6 details of control registers ..................................................................................... vi-1-1 0 0x300380C0x300392 : p x port data registers (pp x _p x d) ..................................................... vi-1-1 1 0x30038 e: p7 port data register (pp7_p7d) ........................................................................ vi-1-1 2 0x300381C0x300393 : p x i/o control registers (pp x _ioc x ) ................................................. vi-1-1 3 0x3003a0C0x3003b3 : p x x port function select registers (pp x _ x x _cfp) ........................... vi-1-1 4 0x3003c0 : port input interrupt select register 1 (ppintsel_spt03) ................................. vi-1-1 5 0x3003c1 : port input interrupt select register 2 (ppintsel_spt47) ................................. vi-1-1 5 0x3003c4 : port input interrupt select register 3 (ppintsel_spt811) ............................... vi-1-1 5 0x3003c5 : port input interrupt select register 4 (ppintsel_spt1215) ............................. vi-1-1 5 0x3003c2: port input interrupt polarity select register 1 (ppintpol_spp07) .................... vi-1-1 7 0x3003c6 : port input interrupt polarity select register 2 (ppintpol_spp815) .................. vi-1-1 7 0x3003c3 : port input interrupt edge/level select register 1 (ppintel_sept07) ............... vi-1-1 8 0x3003c7 : port input interrupt edge/level select register 2 (ppintel_sept815) ............. vi-1-1 8 0x3003d0 : key input interrupt select register (pkintsel_sppk01) .................................. vi-1-1 9 0x3003d2 : key input interrupt (fpk 0 ) input comparison register (pkintcomp_scpk0) ... vi-1-2 0 0x3003d3 : key input interrupt (fpk 1 ) input comparison register (pkintcomp_scpk1) ... vi-1-2 0 0x3003d4 : key input interrupt (fpk0) input mask register (pkintcomp_smpk0) ............ vi-1-2 1 0x3003d5 : key input interrupt (fpk1) input mask register (pkintcomp_smpk1) ............ vi-1-2 1 vi.1.7 precautions .............................................................................................................. vi-1-2 2 vi.2 extended general-purpose i/o ports (egpio) ................................................... vi-2- 1 vi.2.1 structure of egpio port ........................................................................................... vi-2- 1 vi.2.2 selecting the i/o pin functions ................................................................................ vi-2- 1 vi.2.3 i/o control register and i/o modes ......................................................................... vi-2- 2 vi.2.4 egpio operating clock ............................................................................................ vi-2- 3 vi.2.5 details of control registers ...................................................................................... vi-2- 4 0x300c00C0x300c04 : p x i/o control registers (pp x _ioc ) ................................................... vi-2- 5 0x300c01C0x300c05 : p x port data registers (pp x _ data ) ................................................... vi-2- 6 0x300c20C0x300c25 : p x x port function select registers (pp x _cfp0/1 ) ............................. vi-2- 7
contents s1c33e08 technical manual epson xv vii peripheral m odules 5 ( analog ) vii.1 a/d converter (adc) ............................................................................................ vii-1- 1 vii.1.1 features and structure of a/d converter ................................................................ vii-1- 1 vii.1.2 input pins of a/d converter ..................................................................................... vii-1- 2 vii.1.3 a/d converter operating clock ............................................................................... vii-1- 3 vii.1.4 setting a/d converter .............................................................................................. vii-1- 4 vii.1.5 control and operation of a/d conversion ............................................................... vii-1- 9 vii.1.6 a/d converter interrupt and dma ........................................................................... vii-1-1 3 vii.1.7 details of control registers .................................................................................... vii-1-1 5 0x300520 : a/d clock control register (pad_clkctl) ......................................................... vii-1-1 6 0x300540 : a/d conversion result register (pad_add) ....................................................... vii-1-1 7 0x300542 : a/d trigger/channel select register (pad_trig_chnl) ................................... vii-1-1 8 0x300544 : a/d control/status register (pad_en_smpl_stat) .......................................... vii-1-2 0 0x300546 : a/d channel status flag register (pad_end) .................................................... vii-1-2 3 0x300548C0x300550 : a/d ch. x conversion result buffer registers (pad_ch x _buf) ........ vii-1-2 4 0x300558 : a/d upper limit value register (pad_upper) .................................................... vii-1-2 5 0x30055 a: a/d lower limit value register (pad_lower) ................................................... vii-1-2 6 0x30055 c: a/d conversion complete interrupt mask register (pad_ch04_intmask) ...... vii-1-2 7 0x30055 e: a/d converter mode select/internal status register (pad_advmode) ............. vii-1-2 8 vii.1.8 precautions ............................................................................................................. vii-1-2 9
contents xvi epson s1c33e08 technical manual viii peripheral m odules 6 ( lcd ) viii.1 lcd controller (lcdc) ...................................................................................... viii-1- 1 viii.1.1 overview ................................................................................................................ viii-1- 1 viii.1.2 block diagram ........................................................................................................ viii-1- 3 viii.1.3 output pins of the lcd controller ......................................................................... viii-1- 4 viii.1.4 system settings ..................................................................................................... viii-1- 6 viii.1.4.1 configuration of display data memory (vram) ...................................... viii-1- 6 viii.1.4.2 setting the lcdc clock ........................................................................... viii-1- 7 viii.1.5 setting the lcd panel ........................................................................................... viii-1- 9 viii.1.5.1 types of panels ....................................................................................... viii-1- 9 viii.1.5.2 stn panel timing parameters ............................................................... viii-1-1 0 viii.1.5.3 hr-tft panel timing parameters ......................................................... viii-1-1 2 viii.1.5.4 display modes ........................................................................................ viii-1-1 7 viii.1.5.5 look-up tables ....................................................................................... viii-1-2 0 viii.1.5.6 frame rates ........................................................................................... viii-1-2 6 viii.1.5.7 other settings ........................................................................................ viii-1-2 6 viii.1.6 display control ..................................................................................................... viii-1-2 7 viii.1.6.1 controlling lcd power up/down ........................................................... viii-1-2 7 viii.1.6.2 setting the display start address and line address offset ................... viii-1-2 8 viii.1.6.3 writing display data ............................................................................... viii-1-2 9 viii.1.6.4 inverting and blanking the display ......................................................... viii-1-2 9 viii.1.6.5 picture-in-picture plus ............................................................................ viii-1-2 9 viii.1.7 lcdc interrupt and dma ...................................................................................... viii-1-3 2 viii.1.8 power save ........................................................................................................... viii-1-3 4 viii.1.9 details of control registers .................................................................................. viii-1-3 5 0x301a00 : frame interrupt register (plcdc_int) .............................................................. viii-1-3 6 0x301a04 : status and power save configuration register (plcdc_ps) ............................. viii-1-3 7 0x301a10 : horizontal display register (plcdc_hd) ........................................................... viii-1-3 8 0x301a14 : vertical display register (plcdc_vd) ................................................................ viii-1-3 9 0x301a18 : mod rate register (plcdc_mr) ...................................................................... viii-1-4 0 0x301a20 : horizontal display start position register (plcdc_hdps) ................................ viii-1-4 1 0x301a24 : vertical display start position register (plcdc_vdps) .................................... viii-1-4 2 0x301a28 : fpline pulse setup register (plcdc_l) .......................................................... viii-1-4 3 0x301a2 c: fpframe pulse setup register (plcdc_f) .................................................... viii-1-4 4 0x301a30 : fpframe pulse offset register (plcdc_fo) .................................................. viii-1-4 5 0x301a40 : hr-tft special output register (plcdc_tso) ................................................ viii-1-4 6 0x301a44 : tft_ctl1 pulse register (plcdc_tc1) ........................................................... viii-1-4 7 0x301a48 : tft_ctl0 pulse register (plcdc_tc0) ........................................................... viii-1-4 8 0x301a4 c: tft_ctl2 register (plcdc_tc2) .................................................................... viii-1-4 9 0x301a60 : lcdc display mode register (plcdc_dmd) .................................................... viii-1-5 0 0x301a64 : iram select register (plcdc_iram) ................................................................ viii-1-5 3 0x301a70 : main window display start address register (plcdc_madd) ......................... viii-1-5 4 0x301a74 : main window line address offset register (plcdc_mladd) .......................... viii-1-5 5 0x301a80 : sub-window display start address register (plcdc_sadd) ............................ viii-1-5 6 0x301a88 : sub-window start position register (plcdc_ssp) ............................................ viii-1-5 7 0x301a8 c: sub-window end position register (plcdc_sep) ............................................. viii-1-5 8 0x301aa0 : look-up table data register 0 (plcdc_lut_03) .............................................. viii-1-5 9 0x301aa4 : look-up table data register 1 (plcdc_lut_47) .............................................. viii-1-6 0 0x301aa8 : look-up table data register 2 (plcdc_lut_8b) ............................................. viii-1-6 1 0x301 aac: look-up table data register 3 (plcdc_lut_cf) .......................................... viii-1-6 2 viii.1.10 precautions ......................................................................................................... viii-1-6 3
contents s1c33e08 technical manual epson xvii viii.2 ivram and ivram arbiter ................................................................................. viii-2- 1 viii.2.1 ivram ................................................................................................................... viii-2- 1 viii.2.2 ivram arbiter ........................................................................................................ viii-2- 2 viii.2.3 ivram arbiter operating clock ............................................................................. viii-2- 3 viii.2.4 details of the control register ............................................................................... viii-2- 4 0x301a64 : iram select register (plcdc_iram) ................................................................. viii-2- 4
contents xviii epson s1c33e08 technical manual ix peripheral m odules 7 ( usb ) ix.1 usb function controller (usb) ........................................................................... ix-1- 1 ix.1.1 outline of the usb function controller ..................................................................... ix-1- 1 ix.1.2 pins for the usb interface ........................................................................................ ix-1- 2 ix.1.3 usb operating clocks and dma registers .............................................................. ix-1- 3 ix.1.3. 1 controlling the usb clocks ........................................................................ ix-1- 3 ix.1.3. 2 setting the misc register ........................................................................... ix-1- 3 ix.1.3. 3 setting the itc and hsdma controllers .................................................... ix-1- 4 ix.1.4 functional description ............................................................................................. ix-1- 7 ix.1.4. 1 usb control ............................................................................................... ix-1- 8 ix.1.4. 2 fifo management .................................................................................... ix-1-2 5 ix.1.4. 3 port interface ............................................................................................. ix-1-2 8 ix.1.4. 4 snooze ...................................................................................................... ix-1-3 3 ix.1.5 registers .................................................................................................................. ix-1-3 4 ix.1.5.1 list of registers ......................................................................................... ix-1-3 4 ix.1.5.2 detailed description of registers .............................................................. ix-1-3 7 0x300900 : mainintstat (main interrupt status) ....................................................................... ix-1-3 7 0x 3009 01 : sie_intstat (sie interrupt status) ......................................................................... ix-1-3 8 0x 3009 02 : eprintstat (epr interrupt status) .......................................................................... ix-1-3 9 0x 3009 03 : dma_intstat (dma interrupt status) .................................................................... ix-1-4 0 0x 3009 04 : fifo_intstat (fifo interrupt status) .................................................................... ix-1-4 1 0x 3009 07 : ep0intstat (ep0 interrupt status) ......................................................................... ix-1-4 2 0x 3009 08 : epaintstat (epa interrupt status) ......................................................................... ix-1-4 3 0x 3009 09 : epbintstat (epb interrupt status) ......................................................................... ix-1-4 4 0x 30090a : epcintstat (epc interrupt status) ......................................................................... ix-1-4 5 0x 30090b : epdintstat (epd interrupt status) ........................................................................ ix-1-4 6 0x 3009 10 : mainintenb (main interrupt enable) ...................................................................... ix-1-4 7 0x 3009 11 : sie_intenb (sie interrupt enable) ........................................................................ ix-1-4 8 0x 3009 12 : eprintenb (epr interrupt enable) ......................................................................... ix-1-4 9 0x 3009 13 : dma_intenb (dma interrupt enable) ................................................................... ix-1-5 0 0x 3009 14 : fifo_intenb (fifo interrupt enable) ................................................................... ix-1-5 1 0x 3009 17 : ep0intenb (ep0 interrupt enable) ........................................................................ ix-1-5 2 0x 3009 18 : epaintenb (epa interrupt enable) ........................................................................ ix-1-5 3 0x 3009 19 : epbintenb (epb interrupt enable) ........................................................................ ix-1-5 4 0x 30091a : epcintenb (epc interrupt enable) ........................................................................ ix-1-5 5 0x 30091b : epdintenb (epd interrupt enable) ....................................................................... ix-1-5 6 0x 3009 20 : revisionnum (revision number) .......................................................................... ix-1-5 7 0x 3009 21 : usb_control (usb control) ................................................................................. ix-1-5 8 0x 3009 22 : usb_status (usb status) .................................................................................... ix-1-5 9 0x 3009 23 : xcvrcontrol (xcvr control) .................................................................................... ix-1-6 0 0x 3009 24 : usb_test (usb test) ............................................................................................ ix-1-6 1 0x 3009 25 : epncontrol (endpoint control) ............................................................................. ix-1-6 2 0x 3009 26 : eprfifo_clr (epr fifo clear) ............................................................................. ix-1-6 3 0x 30092 e: framenumber_h (frame number high) ............................................................ ix-1-6 4 0x 30092f : framenumber_l (frame number low) .............................................................. ix-1-6 5 0x 3009 30 C0x 3009 37 : ep0setup_0 (ep0 setup 0) Cep0setup_7 (ep0 setup 7 ) .................. ix-1-6 6 0x 3009 38 : usb_address (usb address) .............................................................................. ix-1-6 7 0x 3009 39 : ep0control (ep0 control) ..................................................................................... ix-1-6 8 0x 30093a : ep0controlin (ep0 control in) ............................................................................ ix-1-6 9 0x 30093b : ep0controlout (ep0 control out) .................................................................... ix-1-7 0 0x 30093f : ep0 maxsize (ep0 max packet size) ................................................................... ix-1-7 1 0x 3009 40 : epacontrol (epa control) ..................................................................................... ix-1-7 2 0x 3009 41 : epbcontrol (epb control) ..................................................................................... ix-1-7 3 0x 3009 42 : epccontrol (epc control) ..................................................................................... ix-1-7 4 0x 3009 43 : epdcontrol (epd control) ..................................................................................... ix-1-7 5 0x 3009 50 : epamaxsize_h (epa max packet size high) ..................................................... ix-1-7 6
contents s1c33e08 technical manual epson xix 0x 3009 51 : epamaxsize_l (epa max packet size low) ....................................................... ix-1-7 6 0x 3009 52 : epaconfig_0 (epa configuration 0) ..................................................................... ix-1-7 7 0x 3009 53 : epaconfig_1 (epa configuration 1) ..................................................................... ix-1-7 8 0x 3009 54 : epbmaxsize_h (epb max packet size high) ..................................................... ix-1-7 9 0x 3009 55 : epbmaxsize_l (epb max packet size low) ....................................................... ix-1-7 9 0x 3009 56 : epbconfig_0 (epb configuration 0) ..................................................................... ix-1-8 0 0x 3009 57 : epbconfig_1 (epb configuration 1) ..................................................................... ix-1-8 1 0x 3009 58 : epcmaxsize_h (epc max packet size high) ..................................................... ix-1-8 2 0x 3009 59 : epcmaxsize_l (epc max packet size low) ....................................................... ix-1-8 2 0x 30095a : epcconfig_0 (epc configuration 0) ..................................................................... ix-1-8 3 0x 30095b : epcconfig_1 (epc configuration 1) ..................................................................... ix-1-8 4 0x 30095c : epdmaxsize_h (epd max packet size high) .................................................... ix-1-8 5 0x 30095d : epdmaxsize_l (epd max packet size low) ...................................................... ix-1-8 5 0x 30095 e: epdconfig_0 (epd configuration 0) ..................................................................... ix-1-8 6 0x 30095f : epdconfig_1 (epd configuration 1) ..................................................................... ix-1-8 7 0x 3009 70 : epastartadrs_h (epa fifo start address high) ............................................... ix-1-8 8 0x 3009 71 : epastartadrs_l (epa fifo start address low) ................................................. ix-1-8 8 0x 3009 72 : epbstartadrs_h (epb fifo start address high) ............................................... ix-1-8 9 0x 3009 73 : epbstartadrs_l (epb fifo start address low) ................................................ ix-1-8 9 0x 3009 74 : epcstartadrs_h (epc fifo start address high) ............................................... ix-1-9 0 0x 3009 75 : epcstartadrs_l (epc fifo start address low) ................................................. ix-1-9 0 0x 3009 76 : epdstartadrs_h (epd fifo start address high) ............................................... ix-1-9 1 0x 3009 77 : epdstartadrs_l (epd fifo start address low) ................................................ ix-1-9 1 0x 3009 80 : cpu_joinrd (cpu join fifo read) .................................................................... ix-1-9 2 0x 3009 81 : cpu_joinwr (cpu join fifo write) .................................................................... ix-1-9 3 0x 3009 82 : enepnfifo_access (enable epn fifo access) ................................................. ix-1-9 4 0x 3009 83 : epnfifoforcpu (epn fifo for cpu) .................................................................. ix-1-9 5 0x 3009 84 : epnrdremain_h (epn fifo read remain high) ............................................. ix-1-9 6 0x 3009 85 : epnrdremain_l (epn fifo read remain low) ............................................... ix-1-9 6 0x 300986 : epnwrremain_h (epn fifo write remain high) ............................................. ix-1-9 7 0x 300987 : epnwrremain_l (epn fifo write remain low) ............................................... ix-1-9 7 0x 3009 88 : descadrs_h (descriptor address high) .............................................................. ix-1-9 8 0x 3009 89 : descadrs_l (descriptor address low) ............................................................... ix-1-9 8 0x 30098a : descsize_h (descriptor size high) .................................................................... ix-1-9 9 0x 30098b : descsize_l (descriptor size low) ..................................................................... ix-1-9 9 0x 30098f : descdoor (descriptor door) ................................................................................ ix-1-10 0 0x 3009 90 : dma_fifo_control (dma fifo control) ............................................................ ix-1-10 1 0x 3009 91 : dma_join (dma join fifo) ................................................................................ ix-1-10 2 0x 3009 92 : dma_control (dma control) ............................................................................... ix-1-10 3 0x 3009 94 : dma_config_0 (dma configuration 0) ................................................................ ix-1-10 4 0x 3009 95 : dma_config_1 (dma configuration 1) ................................................................ ix-1-10 5 0x 3009 97 : dma_latency (dma latency) ............................................................................. ix-1-10 6 0x 3009 98 : dma_remain_h (dma fifo remain high) ...................................................... ix-1-10 7 0x 3009 99 : dma_remain_l (dma fifo remain low) ....................................................... ix-1-10 7 0x 30099c : dma_count_hh (dma transfer byte counter high/high) .............................. ix-1-10 8 0x 30099d : dma_count_hl (dma transfer byte counter high/low) ................................ ix-1-10 8 0x 30099e : dma_count_lh (dma transfer byte counter low/high) ................................ ix-1-10 8 0x 30099f : dma_count_ll (dma transfer byte counter low/low) .................................. ix-1-10 8
contents xx epson s1c33e08 technical manual x peripheral m odules 8 ( mp3 ) x.1 mp3 decoder (mp3) ................................................................................................. x-1- 1 x.1.1 overview ..................................................................................................................... x-1- 1 x.1.2 composition of mp3 decoder system ........................................................................ x-1- 3 x.1.2.1 mp3 decoder bios ...................................................................................... x-1- 4 x.1.2.2 hardware resource requirements .............................................................. x-1- 5 x.1.3 usage of mp3 api functions ...................................................................................... x-1- 6 x.1.3.1 high-level mp3 api functions ..................................................................... x-1- 6 x.1.3.2 low-level mp3 api functions ..................................................................... x-1-1 1 x.1.4 mp3 format ............................................................................................................... x-1-1 2 x.1.4.1 mp3 file format .......................................................................................... x-1-1 2 x.1.4.2 mp3 bit stream format ............................................................................... x-1-1 3 x.1.5 details of mp3 decoder bios api ............................................................................ x-1-1 4 x.1.5.1 return values and event values ................................................................. x-1-1 4 x.1.5.2 c33mp3decopen open mp3 decoder ................................................... x-1-1 5 x.1.5.3 c33mp3decclose close mp3 decoder .................................................. x-1-1 8 x.1.5.4 c33mp3 decstart start playback ............................................................ x-1-1 9 x.1.5.5 c33mp3decstop stop playback ............................................................. x-1-2 1 x.1.5.6 c33mp3 decpause pause playback ........................................................ x-1-2 2 x.1.5.7 c33mp3decresume resume playback ................................................. x-1-2 3 x.1.5.8 c33mp3decresync resynchronization .................................................. x-1-2 4 x.1.5.9 transferdata (callback function) set mp3 data .................................... x-1-2 6 x.1.5.10 event (callback function) event handler ............................................. x-1-2 8 x.1.5.11 c33mp3calcstereoprocess stereo process ........................................ x-1-2 9 x.1.5.12 c33mp3calcstereoprocesslsf stereo process for lsf ..................... x-1-3 1 x.1.5.13 c33mp3calcantialias anti alias process ............................................. x-1-3 3 x.1.5.14 c33mp3calcidctlong inverse mdct calculation for long block ......... x-1-3 4 x.1.5.15 c33mp3 calcidctwindow window calculation ....................................... x-1-3 5 x.1.5.16 c33mp3 calcidctshort inverse mdct calculation for short block ........ x-1-3 6 x.1.5.17 c33mp3 calcsubbandsynthesisfdct fast-dct calculation ................. x-1-3 7 x.1.5.18 c33mp3 calcsubbandsynthesiswindow window calculation for sub-band synthesis .................................... x-1-3 8 x.1.5.19 c33mp3 calcsubbandsynthesiswindow2/4/8 window calculation for sub-band synthesis 2/4/8 ........................... x-1-3 9 x.1.6 performance .............................................................................................................. x-1-4 0 x.1.6.1 support formats .......................................................................................... x-1-4 0 x.1.6.2 cpu occupancy ratio ................................................................................ x-1-4 1
contents s1c33e08 technical manual epson xxi appendi x appendix a i/o map ..................................................................................................... ap-a- 1 0x300010C0x300020 misc register (1) .......................................................................... ap-a- 2 0x300260C0x3002 af interrupt controller ....................................................................... ap-a- 3 0x300300C0x30031b card interface .............................................................................. ap-a-1 1 0x300380C0x 3003d5 i/o ports ...................................................................................... ap-a-1 3 0x300520C0x 300 55e a/d converter .............................................................................. ap-a-2 4 0x300660C0x 300 66 c watchdog timer .......................................................................... ap-a-2 7 0x300780C0x3007ea 16- bit timer ................................................................................. ap-a-2 9 0x300900C0x30099f usb function controller .............................................................. ap-a-3 7 0x300b00C0x300b4f serial interface ............................................................................ ap-a-4 7 0x300c00C0x300c25 extended ports ............................................................................ ap-a-5 2 0x300c40C0x300c4d misc register (2) ......................................................................... ap-a-5 4 0x301100C0x301105 intelligent dma ............................................................................ ap-a-5 6 0x301120C0x30119e high -speed dma ........................................................................ ap-a-5 7 0x301500C0x301510 sram controller ......................................................................... ap-a-7 0 0x301600C0x301610 sdram controller ....................................................................... ap-a-7 1 0x301700C0x30171c spi ............................................................................................... ap-a-7 2 0x301800C0x30181c dcsio ......................................................................................... ap-a-7 3 0x301900C0x301928 real time clock .......................................................................... ap-a-7 4 0x301a00C0x301 aac lcd controller ............................................................................. ap-a-7 6 0x301b00C0x301b24 clock management unit .............................................................. ap-a-8 3 0x301c00C0x301c20 i 2 s interface ................................................................................. ap-a-8 7 appendix b differences between c 33 pe core and other c 33 core ......................... ap-b- 1 b .1 instructions .................................................................................................................. ap-b- 1 b .2 registers ...................................................................................................................... ap-b- 2 b .3 address space and other ........................................................................................... ap-b- 2 appendix c development tools ................................................................................. ap-c- 1 c. 1 major development tools ............................................................................................. ap-c- 1 c. 2 precautions on use of s5u1c33001c ........................................................................ ap-c- 2 appendix d boot ......................................................................................................... ap-d- 1 d. 1 boot mode .................................................................................................................. ap-d- 1 d. 2 nand flash boot ........................................................................................................ ap-d- 2 d. 2.1 configuration of nand flash boot system .................................................. ap-d- 2 d. 2.2 nand flash boot sequence ......................................................................... ap-d- 3 d. 2.3 nand flash data .......................................................................................... ap-d- 5 d. 3 nor flash/external rom boot ................................................................................... ap-d- 7 d. 3.1 configuration of nor flash/external rom boot system ............................. ap-d- 7 d. 3.2 nor flash/external rom boot sequence ................................................... ap-d- 7 d. 3.3 reset vector for nor flash/external rom boot .......................................... ap-d- 8 d. 4 spi-eeprom boot ...................................................................................................... ap-d- 9 d. 4.1 configuration of spi-eeprom boot system ................................................ ap-d- 9 d. 4.2 spi-eeprom boot sequence .................................................................... ap-d-1 0 d. 4.3 eeprom data ............................................................................................. ap-d-1 1 d. 5 pc rs232c boot ........................................................................................................ ap-d-1 2 d. 5.1 configuration of pc rs232c boot system ................................................. ap-d-1 2 d. 5.2 pc rs232c boot sequence ....................................................................... ap-d-1 3 d. 5.3 transfer data ................................................................................................ ap-d-1 4 d. 6 precautions ................................................................................................................. ap-d-1 5 appendix e summary of precautions ....................................................................... ap-e- 1 appendix f supplementary description for clock control .................................... ap-f- 1
i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 s1c33e08 technical manual i s1c33e08 specifications
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.1 overview the s 1c33e08 is a high cost performance 32 -bit risc controller for specific applications that require an mp3 player, several general-purpose i/o ports, a powerful pwm timer/counter function, several serial interfaces includ - ing usb-fs device controller, an adc and a lcd display system, such as middle range electronic dictionaries and educational products with voice/music playback function. the s 1c33e08 consists of a 32 -bit risc cpu-core, an mp3 decoder supporting layer iii specifications, a generic dma controller, a usb-fs device controller, a pwm control timer/counter, several interfaces (sio including irda 1.0 and iso7816-3 protocol, spi, i 2 s and dcsio), an adc, ram/shared ivram and rtc implemented by epson soc design technology using 0.18 m mixed analog low cmos process. table i.1.1 product line model s1c33e08f00a ??? s1c33e08b00a ??? s1c33e08d00a ??? pa ck ag e qfp24-144pin pfbga-180pin die fo rm note : the epson s1c33e08 incorporates mp3 technology of which thomson sa in france holds the patent. manufacturers using the epson s1c33e08 to develop mp3 products must pay royalties to thomson sa in order to procure the license for the mp3 technology. the main functions and features of the s1c33e08 are outlined below. technology ? 0.18 m al-4 -layers mixed analog low power cmos process technology cpu ? epson original c33 pe 32 -bit risc cpu-core with amba bus optimized for soc ? max. 60 mhz operation ? internal 2-stage pipeline and 4 instruction queues ? instruction set: 128 instructions (16 -bit fixed length) ? basic instructions are compatible with the s1c33 32-bit risc cores. ? dual amba bus system for cpu and lcdc internal memories ? 8k-byte ram (1 k bytes are available when the mp3 decoder bios is used) ? 12 k-byte ivram (used as general-purpose ram, vram, or mp3 work area) ? 2k-byte dst ram (used as general-purpose ram or idma descriptor table ram) oscillator circuit / pll osc oscillator circuit ? crystal oscillation: 5 mhz min. to 48 mhz max. ? ceramic oscillation: 48 mhz, fixed ? external clock input: 5 mhz min. to 48 mhz max. ? a 48 mhz clock source with 0.25 % of accuracy should be connected for using the usb function. pll ? pll input frequency: 5 mhz min. to 50 mhz max. (osc3 1, 1/2, 1/3, ... 1/9, 1/10) ? pll output frequency: 20 mhz min. to 90 mhz max. ? multiplication rate: 1, 2, 4, 8, 10, 15 1 ? crystal oscillation: 32.768 khz typ. ? external clock input: 32.768 khz typ.
i s1c33e08 specifications: overview i-1-2 epson s1c33e08 technical manual high speed bus (hb) modules sramc (sram controller) ? 25-bit address lines and 8/16 -bit selectable data bus ? up to a 512m-byte (a[24:0 ]) address space is provided for each chip enable signal. ? max. 8 chip enable signals are available to connect external devices. ? programmable bus wait cycle (0 to 7 cycles) ? supports external wait signals. ? 4 gb physical address space is available. - the physical address space is divided into 23 areas: area 0 to area 22. - areas 0 to 4 and area 6 are system reserved. ? supports only little-endian access to each area. ? memory mapped i/o ? supports both a0 and bs (bus strobe) access type external devices. ? sram, rom, and flash rom direct access interfaces are built in. sdramc (sdram controller with sdram app and ahb local bus arbiter) ? supports sdram direct interface. ? supports only sdram devices with 16 -bit data bus. minimum configuration: 16m bits (2mb), 16-bit sdram 1 maximum configuration: 512m bits (64mb), 16-bit sdram 1 ? cas latency: 1, 2 or 3 programmable ? supports burst and single read/write. ? supports dqm (byte write) function. ? supports max. 4 sdram banks and bank active mode. ? incorporates a 12 -bit auto-refresh counter. ? intelligent self-refresh function for low power operation ? 2-stage 32 -bit data buffer and 8-stage 16-bit 2 -slot instruction buffer built-in ? supports up to 90 mhz sdram clock. - when the cpu clock is 48 mhz, the sdram clock can be set to 48 mhz. - when the cpu clock is 45 mhz, the sdram clock can be set to 90 mhz using the pll. ? arbitrates ownership of the external bus between the cpu, dmac, lcdc and sramc. dmac (direct memory access controller) ? 4 -ch. high speed hardware dma ? 128 -ch. intelligent dma (variable data transfer controller) with specific control table ivramarb (internal video ram arbiter) ? contains a 12kb sram (3,072 words 16 bits 2). ? arbitrates accesses from the lcdc and cpu. ? allows the cpu and lcdc to access ivram in minimum 2 cycles by 32-bit access. ? supports uma (unified memory access) for display. ? ivram is configurable as a 12 kb general-purpose ram in area 0 using a control register if it is not used as a video ram. peripheral bus (sapb) modules tcu (timer/counter unit with pwm outputs) ? 6-ch. 16-bit timer/counter ? supports pwm outputs with da16 (digital d/a) mode. ? contains a prescaler, which can divide the peripheral clock by 1 to 4,096 , to generate the operating clock for each channel. ? possible to invoke dma transfer. wdt (watchdog timer) ? 30 -bit watchdog timer to generate an nmi interrupt ? the watchdog timer overflow cycle (nmi interrupt cycle) is programmable. ? the watchdog timer overflow signal can be output outside the ic.
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 adc (a/d converter) ? 5-ch. 10 -bit a/d converter ? upper/lower limit interrupt is available. ? each adc channel includes a data buffer. ? contains a prescaler, which can divide the peripheral clock by 2 to 256 , to generate the operating clock for adc. itc (interrupt controller) ? possible to invoke dma transfer ? dma controller interrupt: 5 types ? input interrupt: 18 types ? tcu interrupt: 12 types ? efsio interrupt: 9 types ? adc interrupt: 2 types ? rtc interrupt: 1 type ? spi interrupt: 3 types ? dcsio interrupt: 1 type ? usb interrupt: 2 types ? i 2 s interrupt: 1 type ? lcdc interrupt: 1 type gpio (general-purpose i/o ports) ? max. 82 ports in the qfp24-144pin model. * the s 1c33e08 gpio ports are shared with other peripheral function pins (efsio, pwm etc.). there - fore, the number of gpio ports depends on the peripheral functions used. usb (universal serial bus 2.0 compliant full-speed device controller) ? supports usb2.0 full speed (12m bps) mode. ? supports auto negotiation function. ? supports control, bulk, isochronous and interrupt transfers. ? supports 4 general-purpose end points and end point 0 (control). ? embedded 1k-byte programmable fifo ? supports 8 -bit local bus dma port. ? possible to invoke dma transfer. ? supports async. dma transfer. ? supports dma slave mode. ? fixed 48 mhz clock for usb-fs. ? supports snooze mode. rtc (real time clock) ? contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). ? bcd data can be read from and written to both counters. ? capable of controlling the starting and stopping of time clocks . ? 24-hour or 12-hour mode can be selected. ? a 30 -second correction function can be implemented in software. ? periodic interrupts are possible. card (serial input/output with direction control) ? provides smartmedia i/f signals (#smre, #smwe). ? provides 8- or 16 -bit nand flash i/f signals. ? ecc function is available when reading/writing from/to nand flash type devices. ? supports nand flash booting function. ? supports epson middleware fs33.
i s1c33e08 specifications: overview i-1-4 epson s1c33e08 technical manual efsio (extended serial interface with fifo buffer) ? 3 -ch. clock sync./async. serial interface ? contains fifo data buffers (4 receive data buffer and 2 transmit data buffer are available for each chan - nel). ? supports irda1.0 interface. ? contains a baud-rate generator (12-bit programmable timer). ? supports iso7816 mode (ch.1 only). - alternative msb or lsb - memory card interface compatible with iso 7816-3 t=0 & t=1 protocol - programmable baud-rate and guard-time generation - iso 7816 acknowledge and automatically repeat transmission ? possible to invoke dma transfer. spi (serial peripheral interface) ? 1 ch. spi that operates in either master or slave mode ? supports 1- to 32 -bit data transfer. ? data transfer timing (clock phase and polarity variations) is selectable from among 4 types. ? a 1 to 65,536 clocks of delay can be inserted between transfers. ? generates transmit data register empty and receive data register full interrupts. ? supports both mmc and sd-card capabilities. ? possible to invoke dma transfer. dcsio (direction control serial input/output port) ? 2-ch. input/output ports with a serial shifter ? input/output level detection to drive a state machine ? 1-wire or 2 -wire communication protocol is simulated with software. egpio (extended gpio) ? max. 17 configurable gpio ports are available in addition to the standard gpio ports. in die form, max. 91 ports are available. * the egpio ports are shared with other peripheral function pins. therefore, the number of egpio ports depends on the peripheral functions used. ? most ports have a pull-up resistor that can be enabled/disabled with the control register. ? possible to drive the ports low. cmu (extended clock management unit) ? controls clock supply to each peripheral module (static). ? manages reset and nmi inputs. ? switches the system clock source (mclk, sdram_clk, or rtc_clk). ? controls the mclk and rtc_clk oscillator circuits. ? turns on/off and controls frequency multiplication rate of the pll. ? controls clocks according to the standby mode (sleep and halt). ? controls divide ratios of the lcdc clock. ? manages the external bus clock. misc (misc. setting register) ? usb/rtc wait configuration registers ? debug port function select register ? boot mode configuration register i 2 s (inter-ic sound bus interface) ? supports universal audio i 2 s bus interface. ? operates as the master to generate the bit clock, word-select signal, data and master clock. ? generates the i 2 s interrupt signal. ? possible to invoke dma transfer.
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 lcdc (stn/tft lcd controller with amba bus) vram: ? built-in a 12 kb ram usable as a display buffer or general-purpose ram (register selectable) ? supports the uma method allowing lcdc to access sdram (external vram) or ivram (internal vram). ? the external vram map (sdram) is configurable. ? the sub-window area can be located in ivram or external vram regardless of whether it contains the main window area or not. display support: ? 4- or 8 -bit monochrome lcd interface ? 4- or 8 -bit color lcd interface ? single-panel, single-drive passive displays ? 12 -bit generic hr-tft interface - 320 240 -dot sharp hr-tft panel, sii liquid tft panel, or some other tft panels ? typical resolutions - 320 240 (8 -bpp mode, external vram is required) bpp = bits per pixel - 320 240 (1-bpp mode) * note that the panel width must be a multiple of 16 bits per pixel. display modes: ? due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a mono - chrome passive lcd panel is used. - two-shade display in 1-bpp mode - four-shade display in 2-bpp mode - 16-shade display in 4-bpp mode ? a maximum of 64 k colors can be simultaneously displayed on a color passive lcd panel. - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode - 64k-color display in 16-bpp mode ? a maximum of 4096 colors can be simultaneously displayed on a tft panel. - two-color display in 1-bpp mode - four-color display in 2-bpp mode - 16-color display in 4-bpp mode - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode ? a look-up table, which consists of 6 bits 16 entries 3 colors, is provided. - in monochrome 1/2/4-bpp or color 8/12-bpp mode, the look-up table can be used or bypassed. - in color 1/2/4/16-bpp mode, the look-up table cannot be used (must be bypassed). display features: ? picture-in-picture plus (pip + ) picture-in-picture plus enables a secondary window (or sub-window) within the main display window. the sub-window may be positioned anywhere within the main window and is controlled through regis - ters. the sub-window retains the same color depth as the main window. the speed of generating a sub-window by hardware is faster than software. by using this pip + function, it can greatly speed the gui performance and cpu can have more performance to assign other processing. (e.g. voice etc.) ? 12 -bit generic hr-tft interface the 12 -bit generic hr-tft interface can support 320 240 sharp hr-tft panel, sii tft panel or some other tft panels. because the timing of fpfram, fpline, and tft_ctl 0C3 are not fixed for tft panels, they can be controlled by register setting. by different register settings, you can get your specified tft i/f signal timing. ? clock source the lcdc clock can be internally divided 48 mhz by 1 to 16 . the clock division register is located in cmu part.
i s1c33e08 specifications: overview i-1-6 epson s1c33e08 technical manual mp 3 decoder ? mp3 decoder bios provides mp3 decode and playback api functions. - main apis for playback: start playback, stop playback, pause playback, resume playback - main apis for decoding: stereo processing, anti alias processing, idct calculation, sub-band analysis ? sampling frequency: 32, 44.1, and 48 khz (mpeg1 audio layer-iii) 16, 22.05, and 24 khz (mpeg2 audio layer-iii lsf) * the higher the sampling frequency, the more the cpu occupancy rate during playback increases. the cpu clock frequency should be set as high as possible to perform parallel processing using the rtos, etc. ? bit-rate: 32 to 320 kbps (mpeg1 audio layer-iii, cbr/vbr/abr) 8 to 160 kbps (mpeg2 audio layer-iii lsf, cbr/vbr/abr) ? channel mode: stereo (joint stereo and dual channel) and monaural ? sound quality mode: high/middle/low * the sound quality mode affects the cpu occupancy rate. ? cpu occupancy rate: the cpu occupancy rate depends on the cpu clock frequency, sound quality mode, mp 3 data sampling frequency and bit-rate, however, the s1c33e08 is ca - pable of multitask operations under a real-time os such as the rtos even in mp 3 playback. example) when cpu clock = 48 mhz, sampling frequency = 44.1 khz and sound quality mode = middle, the mp 3 decode/playback processing occupies the cpu for about 18 ms in about 26 ms cycles (cpu occupancy rate: 70% or less). ? a built-in hardware mp3 accelerator * when using the mp 3 decoder bios (mp3 decoder module), a 7 kb internal ram area, 12 kb ivram, a 20 kb external ram area (min.), and a 40 -byte stack area are required. when using the mp3 calculation module only, a 40-byte stack area is required. operating voltage ? v dd (core): 1.70 to 1.90 v (typ. 1.8 v) when a ceramic resonator is used for the usb clock ? v dd (core): 1.65 to 1.95 v (typ. 1.8 v) when a crystal is used or an external clock is input ? plv dd : 1.65 to 1.95 v (typ. 1.8 v) ? v ddh (i/o): 2.70 to 3.60 v when the usb is not used (5-v tolerant i/o not supported) ? v ddh (i/o): 3.00 to 3.60 v (typ. 3.3 v) when the usb is used (5-v tolerant i/o not supported) operating frequency ? cpu: 60 mhz max. ? usb: 48 mhz fixed. ? sdramc: 90 mhz max. ? lcdc: 60 mhz max. ? other peripheral circuits: 60 mhz max. operating temperatures ? -40 to 85 c ( 0 to 70 c when a ceramic resonator is used for the usb clock)
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 current consumption ? during sleep: 1.0 a typ. (operation clock = 48 mhz) ? during halt: 3.0 ma typ. (operation clock = 48 mhz) ? during execution: core 19.0 ma typ. (operation clock = 48 mhz) sramc 3.4 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) sdramc 5.4 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) dma 3.9 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) lcdc 5.3 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) usb 10.0 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) adc 260.0 a typ. (idle state when adc is enabled) mp 3 decoder 8.0 ma typ. (when mp3 decoder is on playback) * by controlling the cpu clock through the clock-gear (cmu), c urrent consumption can be reduced. shipping form ? package: qfp24-144pin (16 mm 16 mm 1.0 mm and 0.4 mm pin pitch) pfbga- 180pin (12 mm 12 mm 1.2 mm and 0.8 mm ball pitch) ? die form: 168 pads with pad pitch 90 m
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i s1c33e08 specifications: block diagram s1c33e08 technical manual epson i-2-1 i block i.2 block diagram a0ram (ivram) (12kb) a0ram (8kb) area 0 specific ro m (mp3 decoder bios) a18m pll cmu sdramc register s sramc register s i 2 s dcsio lcdc register s rt c spi pe_e08_cpu (hardw are mp3 accelerator b uilt-in) lcdc area 1 area 6 ivram (12kb) ivram arbiter dqb dqb arbiter iqb dst ram (2kb) area 3 gate ro m (4 wo r ds) area 10 sdramc_ip mux exter nal memor y i/f a6dec (used as a ram or mp3 wo rk area) (the mp3 decoder bios requires a 20kb or more e xter nal ram area.) the mp3 decoder bios uses ivram (area 0) as an mp3 wo rk area. a6_x32 de vices dma gp register s tcu16 (6 ch.) wdt adc a6_x16 de vices gpio egpio efsio (3 ch.) itc card i/f misc register s usb a6_x8 de vices sd app1 < < < x32 < < cpu_ahb lcdc_ahb lcdc_amb a: master dma gp: master 2 s1c33pe_amb a: master 1 (used as a vram) sd app2 sdramc sramc (sapb bridge) hsdma idma dma gp registers dma gp external ram x32 x32 x32 x32 x32 x16 x16 x16 x32 figure i.2.1 s1c33e08 block diagram
i s1c33e08 specifications: block diagram i-2-2 epson s1c33e08 technical manual this page is blank.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3 pin description i.3.1 pin arrangement the s1c33e08 comes in a qfp24-144pin or pfbga-180pin plastic package. i.3.1.1 qfp package pin arrangement (s1c33e08f00a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (p55/card0) #ce9 (p46/tft_ctl2) a18 (p45/fpdat11) a19 (p44/fpdat10) a20 (p43/fpdat9) a21 (p42/fpdat8) a22 v ss (card2/#dmareq0) p30 (card3/#dmareq1) p31 (card4/#dmareq2) p32 (card5/#dmareq3) p33 (sin0/#dmaack2) p00 (sout0/#dmaack3) p01 (#sclk0/#dmaend2) p02 (#srdy0/#dmaend3) p03 v ddh (sin1/i2s_sdo) p04 (sout1/i2s_ws) p05 (#sclk1/i2s_sck) p06 (#srdy1/i2s_mclk) p07 (tm0/sin0/#dmaend0) p10 (tm1/sout0/#dmaend1) p11 v dd (tm2/#sclk0/#dmaack0) p12 (tm3/#srdy0/#dmaack1) p13 (tm4/sin1) p14 (p15/tm5/sout1/tft_ctl0) dst0 (p16/dcsio0/#sclk1/tft_ctl3) dst1 (p17/dcsio1/#srdy1/tft_ctl2) dpco v ddh (p34) dsio (p36) dst2 (p35) dclk (#wait/excl2) p64 (sdi/fpdat8) p65 (sdo/fpdat9) p66 p25 (#sdwe) p24 (#sdcas) p23 (#sdras/tft_ctl1) v ddh p22 (#sdcs) sdclk (p21) p20 (sdcke) v ss d15 d14 d13 d12 v dd d11 d10 d9 d8 v ddh d7 d6 d5 d4 v dd d3 d2 d1 d0 v ss p63 (#srdy2/wdt_clk/#wdt_nmi) p62 (#sclk2/#adtrg/cmu_clk) p61 (sout2/dcsio1/excl1) p60 (sin2/dcsio0/excl0) usbvbus usbdp usbdm #nmi 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 #reset p97 (fpdat7) p96 (fpdat6) p95 (fpdat5) p94 (fpdat4) v ddh p93 (fpdat3) p92 (fpdat2) p91 (fpdat1) p90 (fpdat0) v ss mclko mclki v dd p85 (dcsio1) p84 (dcsio0/fpdat11) p83 (fpdrdy/tft_ctl1/bclk) p82 (fpshift) p81 (fpline) p80 (fpframe) p70 (ain0) p71 (ain1) p72 (ain2) p73 (ain3) p74 (ain4/excl5) av dd boot1 test0 plv dd vcp plv ss v ss rtc_clko rtc_clki v dd p67 (spi_clk/fpdat10) (dqml) p26 (dqmh) p27 a14 a15 a16 / dqml a17 / dqmh (p53/sda10) #ce7 a0 / #bsl v ss a1 a2 a3 a4 a5 v dd a6 a7 a8 a9 v ddh a10 (p47) a11 a12 a13 (p41/#sdras/excl3) a23 (p40/#sdcas/excl4) a24 v ss (p57) #ce10 #rd #wrl #wrh / #bsh (p56) #ce11 (bclk/#ce6/cmu_clk) p52 (p50/card0) #ce4 (p51/card1) #ce5 (p54/card1) #ce8 figure i.3.1.1.1 pin arrangement (qfp24-144pin)
i s1c33e08 specifications: pin description i-3-2 epson s1c33e08 technical manual i.3.1.2 pfbga package pin arrangement (s1c33e08b00a) top view bottom view a1 corner a1 corner index a b c d e f g h j j l m n p a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 n.c. a18 p46 tft_ctl2 a22 p42 fpd at 8 p30 card2 #dmareq0 p33 card5 #dmareq3 p03 #srd y0 #dmaend3 p06 #sclk1 i2s_sck p10 tm0 sin0 #dmaend0 dst0 p15 tm5 sout1 tft_ctl0 dsio p34 dclk p35 pb3 fpd a t11 i2s_mclk card5 p67 spi_clk fpd a t10 n.c . a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 1 #ce8 p54 card1 #ce9 p55 card0 a20 p44 fpd a t10 a19 p45 fpd a t11 p00 sin0 #dmaa ck2 p01 sout0 #dmaa ck3 p04 sin1 i2s_sdo p11 tm1 sout0 #dmaend1 p13 tm3 #srd y0 #dmaa ck1 dpco p17 dcsio1 #srd y1 tft_ctl2 pb0 fpd at 8 i2s_sdo card2 p65 sdi fpd at 8 r tc_clki #ce4 p50 card0 #ce5 p51 card1 a21 p43 fpd at 9 p31 card3 #dmareq1 p02 #sclk0 #dmaend2 p05 sout1 i2s_ws p07 #srd y1 i2s_mclk p14 tm4 sin1 dst1 p16 dcsio0 #sclk1 tft_ctl3 p64 #w ait excl2 pb2 fpd a t10 i2s_sck card4 p66 sdo fpd at 9 r tc_clk o #ce11 p56 #wrh/ #bsh p52 bclk #ce6 cmu_clk p32 card4 #dmareq2 p12 tm2 #sclk0 #dmaa ck0 dst2 p36 pb1 fpd at 9 i2s_ws card3 test0 vcp #rd a23 p41 #sdras excl3 a11 p47 a8 a4 #ce10 p57 #wrl boot1 p73 ain3 p74 ain4 excl5 p24 #sdcas p22 #sdcs sdclk p21 d15 d8 d6 d4 d1 p63 #srd y2 wdt_clk #wdt_nmi usbvbus usbdp usbdm a13 a24 p40 #sdcas excl4 p81 fpline p71 ain1 p70 ain0 a10 a12 p82 fpshift p83 fpdrd y tft_ctl1 bclk p72 ain2 p80 fpframe a6 a9 p84 dcsio0 fpd a t11 p85 dcsio1 mclki a2 a3 a7 burnin mclko p26 dqml p25 #sd we p23 #sdras tft_ctl1 p20 sdcke d12 d9 d7 d3 d0 boot0 p60 sin2 dcsio0 excl0 #nmi #reset pa 4 fpd a t11 tft_ctl3 card1 a14 p27 dqmh d14 d13 d10 d11 d5 d2 p62 #sclk2 #adtrg cmu_clk p61 sout2 dcsio1 excl1 pa 2 fpd at 9 tft_ctl1 p97 fpd at 7 p96 fpd at 6 pa 3 fpd a t10 tft_ctl2 card0 a15 a0/ #bsl a16/ dqml p91 fpd at 1 p94 fpd at 4 pa 1 fpd at 8 tft_ctl0 pa 0 tft_ctl0 #ce7 p53 sd a10 a17/ dqmh a1 a5 p90 fpd at 0 p93 fpd at 3 p95 fpd at 5 p92 fpd at 2 2 3 4 5 6 7 8 9 10 plv dd 11 12 plv ss 13 n.c. v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh av dd n.c. 14 2 3 4 5 6 7 8 t op vie w 9 1 0 1 1 1 2 1 3 1 4 v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd v ss v ss v ss v ss v ss v ss v ss figure i.3.1.2.1 pin arrangement (pfbga-180pin)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.2 pin functions tables i. 3.2.1 to i.3.2.6 list the function of each pin on the s1c33e08. table i.3.2.1 power supply pin list function po wer supply (+) f or core (1.8 v) po wer supply (+) f or i/o (3.3 v) po wer supply (C); gnd po wer supply (+) f or pll (pl v dd = v dd ) po wer supply (C) f or pll (pl v ss = v ss ) po wer supply (+) f or analog system and ain0Cain4 (3.3 v, av dd = v ddh ) qfp 23,38,59,86,96,123 16,30,67,91,105,128 7,41,62,81,101,117,135 44 42 47 pin no. pin name v dd v ddh v ss pl v dd pl v ss av dd pfbga d7,e6,e7,f10,f11,g4, g11,h4,h5,k7,n2,n8 d8,e8,e9,f4,f5,g5,g10, h10,h11,k8,k9,l9 d4,d5,d6,d11,e5,e10, e11,j5,j10,j11,k5,k6, k10,k11,n3,n9 p5 p4 p6 table i.3.2.2 clock pin list i/o i o i o o pull- up/do wn C C C C C function high speed (osc3) oscillation input (cr ystal/ceramic oscillator or e xter nal cloc k input with v dd le v el) high speed (osc3) oscillation output real time cloc k (osc1) oscillation input (cr ystal/ceramic oscillator or e xter nal cloc k input with v dd le v el) real time cloc k (osc1) oscillation output pll analog monitor (used f or current monitor) qfp 60 61 39 40 43 pin no. pin name mclki mclk o r tc_clki r tc_clk o vcp pfbga p8 p9 p2 p3 n4 table i.3.2.3 external bus pin list i/o i /o i /o i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) pull- up/do wn ? 2 ? 2 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function data b us (d7Cd0) d[15:8]: data b us (d15Cd8) pc[7:0]: extended general-pur pose i/o por ts address b us (a0) or b us strobe (lo w b yte) signal address b us (a10Ca1) a11: address b us (a11) (def ault) p47: general-pur pose i/o por t address b us (a15Ca12) address b us (a16) or sdram data (lo w b yte) input/output mask signal output address b us (a17) or sdram data (high b yte) input/output mask signal output a18: address b us (a18) (def ault) p46: general-pur pose i/o por t tft_ctl2: lcdc tft i/f control signal 2 output a19: address b us (a19) (def ault) p45: general-pur pose i/o por t fpd a t11: lcd data a20: address b us (a20) (def ault) p44: general-pur pose i/o por t fpd a t10: lcd data a21: address b us (a21) (def ault) p43: general-pur pose i/o por t fpd a t9: lcd data qfp 90C87, 85C82 100C97, 95C92 116 129, 127C124, 122C118 130 112,111, 132,131 113 114 2 3 4 5 pin no. pin name d[7:0] d[15:8] pc[7:0] a0 / #bsl a[10:1] a11 p47 a[15:12] a16 / dqml a17 / dqmh a18 p46 tft_ctl2 a19 p45 fpd a t11 a20 p44 fpd a t10 a21 p43 fpd at 9 pfbga g13,g14, g12,h14, h13,h12, j14,j13 e14,c12, d12,e13, f12,e12, f13,f14 b11 b7,c8, a8,d9, b8,d10, a9,c9, b9,c10 a7 a11,a12, b6,c7 c11 b10 b1 d2 c2 c3
i s1c33e08 specifications: pin description i-3-4 epson s1c33e08 technical manual i/o i/ o (h) i/ o (h) i/ o ( l) o o o ? 3 i/ o (h) i/ o (h) i /o (pu) i/ o (h) i/ o (h) i/ o (h) i/ o (h) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function a22: address b us (a22) (def ault) p42: general-pur pose i/o por t fpd a t8: lcd data a23: address b us (a23) (def ault) p41: general-pur pose i/o por t #sdras: sdram ro w address strobe signal output excl3: 16-bit timer 3 ev ent counter input a24: address b us (a24) (def ault) p40: general-pur pose i/o por t #sdcas: sdram column address strobe signal output excl4: 16-bit timer 4 ev ent counter input read signal wr ite (lo w b yte) signal wr ite (high b yte) signal or b us strobe (high b yte) signal #ce10: chip enab le signal f or areas 10, 13 and 20 (def ault) p57: general-pur pose i/o por t #ce4: chip enab le signal f or areas 4 and 14 (def ault) p50: general-pur pose i/o por t card0: card i/f signal 0 output #ce5: chip enab le signal f or areas 5, 15 and 16 (def ault) p51: general-pur pose i/o por t card1: card i/f signal 1 output p52: general-pur pose i/o por t (def ault) bclk: bus cloc k output #ce6: chip enab le signal f or areas 6, 17 and 18 cmu_clk: cmu e xter nal cloc k output #ce7: chip enab le signal f or areas 7 and 19 (def ault) p53: general-pur pose i/o por t sd a10: sdram address bit 10 #ce8: chip enab le signal f or areas 8 and 21 (def ault) p54: general-pur pose i/o por t card1: card i/f signal 1 output #ce9: chip enab le signal f or areas 9 and 22 (def ault) p55: general-pur pose i/o por t card0: card i/f signal 0 output #ce11: chip enab le signal f or areas 11 and 12 (def ault) p56: general-pur pose i/o por t p20: general-pur pose i/o por t (def ault) sdcke: sdram cloc k enab le signal output sdclk: sdram cloc k output (def ault) p21: general-pur pose i/o por t p22: general-pur pose i/o por t (def ault) #sdcs: sdram chip enab le signal output p23: general-pur pose i/o por t (def ault) #sdras: sdram ro w address strobe signal output tft_ctl1: lcdc tft i/f control signal 1 output p24: general-pur pose i/o por t (def ault) #sdcas: sdram column address strobe signal output p25: general-pur pose i/o por t (def ault) #sd we: sdram wr ite signal output p26: general-pur pose i/o por t (def ault) dqml: sdram data (lo w b yte) input/output mask signal output p27: general-pur pose i/o por t (def ault) dqmh: sdram data (high b yte) input/output mask signal output qfp 6 133 134 137 138 139 136 142 143 141 115 144 1 140 102 103 104 106 107 108 109 110 pin no. pin name a22 p42 fpd at 8 a23 p41 #sdras excl3 a24 p40 #sdcas excl4 #rd #wrl #wrh / #bsh #ce10 p57 #ce4 p50 card0 #ce5 p51 card1 p52 bclk #ce6 cmu_clk #ce7 p53 sd a10 #ce8 p54 card1 #ce9 p55 card0 #ce11 p56 p20 sdcke sdclk p21 p22 #sdcs p23 #sdras tft_ctl1 p24 #sdcas p25 #sd we p26 dqml p27 dqmh pfbga c1 a6 c6 a5 c5 b4 b5 a3 b3 c4 a10 a2 b2 a4 d13 d14 c14 c13 b14 b13 a13 b12
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i.3.2.4 input/output port and peripheral circuit pin list i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i/ o (h) i/ o (h) i/ o (h) i /o (hi-z) i /o (hi-z) i /o (hi-z) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p00: general-pur pose i/o por t (def ault) sin0: ser ial i/f ch.0 data input #dmaa ck2: hsdma ch.2 ac kno wledge signal output p01: general-pur pose i/o por t (def ault) sout0: ser ial i/f ch.0 data output #dmaa ck3: hsdma ch.3 ac kno wledge signal output p02: general-pur pose i/o por t (def ault) #sclk0: ser ial i/f ch.0 cloc k input/output #dmaend2: hsdma ch.2 end-of-transf er signal output p03: general-pur pose i/o por t (def ault) #srd y0: ser ial i/f ch.0 ready input/output #dmaend3: hsdma ch.3 end-of-transf er signal output p04: general-pur pose i/o por t (def ault) sin1: ser ial i/f ch.1 data input i2s_sdo: i 2 s send data signal p05: general-pur pose i/o por t (def ault) sout1: ser ial i/f ch.1 data output i2s_ws: i 2 s word select signal p06: general-pur pose i/o por t (def ault) #sclk1: ser ial i/f ch.1 cloc k input/output i2s_sck: i 2 s ser ial cloc k signal p07: general-pur pose i/o por t (def ault) #srd y1: ser ial i/f ch.1 ready input/output i2s_mclk: i 2 s master cloc k signal p10: general-pur pose i/o por t (def ault) tm0: 16-bit timer 0 output sin0: ser ial i/f ch.0 data input #dmaend0: hsdma ch.0 end-of-transf er signal output p11: general-pur pose i/o por t (def ault) tm1: 16-bit timer 1 output sout0: ser ial i/f ch.0 data output #dmaend1: hsdma ch.1 end-of-transf er signal output p12: general-pur pose i/o por t (def ault) tm2: 16-bit timer 2 output #sclk0: ser ial i/f ch.0 cloc k input/output #dmaa ck0: hsdma ch.0 ac kno wledge signal output p13: general-pur pose i/o por t (def ault) tm3: 16-bit timer 3 output #srd y0: ser ial i/f ch.0 ready input/output #dmaa ck1: hsdma ch.1 ac kno wledge signal output p14: general-pur pose i/o por t (def ault) tm4: 16-bit timer 4 output sin1: ser ial i/f ch.1 data input dst0: dst0 signal output f or deb ugging (def ault) p15: general-pur pose i/o por t tm5: 16-bit timer 5 output sout1: ser ial i/f ch.1 data output tft_ctl0: lcdc tft i/f control signal 0 output dst1: dst1 signal output f or deb ugging (def ault) p16: general-pur pose i/o por t dcsio0: dcsio por t #sclk1: ser ial i/f ch.1 cloc k input/output tft_ctl3: lcdc tft i/f control signal 3 output dpco: dpco signal output f or deb ugging (def ault) p17: general-pur pose i/o por t dcsio1: dcsio por t #srd y1: ser ial i/f ch.1 ready input/output tft_ctl2: lcdc tft i/f control signal 2 output p30: general-pur pose i/o por t (def ault) card2: card i/f signal 2 output #dmareq0: hsdma ch.0 request input p31: general-pur pose i/o por t (def ault) card3: card i/f signal 3 output #dmareq1: hsdma ch.1 request input p32: general-pur pose i/o por t (def ault) card4: card i/f signal 4 output #dmareq2: hsdma ch.2 request input qfp 12 13 14 15 17 18 19 20 21 22 24 25 26 27 28 29 8 9 10 pin no. pin name p00 sin0 #dmaa ck2 p01 sout0 #dmaa ck3 p02 #sclk0 #dmaend2 p03 #srd y0 #dmaend3 p04 sin1 i2s_sdo p05 sout1 i2s_ws p06 #sclk1 i2s_sck p07 #srd y1 i2s_mclk p10 tm0 sin0 #dmaend0 p11 tm1 sout0 #dmaend1 p12 tm2 #sclk0 #dmaa ck0 p13 tm3 #srd y0 #dmaa ck1 p14 tm4 sin1 dst0 p15 tm5 sout1 tft_ctl0 dst1 p16 dcsio0 #sclk1 tft_ctl3 dpco p17 dcsio1 #srd y1 tft_ctl2 p30 card2 #dmareq0 p31 card3 #dmareq1 p32 card4 #dmareq2 pfbga e2 f2 e3 f1 g2 f3 g1 g3 h1 h2 j4 j2 h3 j1 j3 k2 d1 d3 e4
i s1c33e08 specifications: pin description i-3-6 epson s1c33e08 technical manual i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i (hi-z) i (hi-z) i (hi-z) i (hi-z) i (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p33: general-pur pose i/o por t (def ault) card5: card i/f signal 5 output #dmareq3: hsdma ch.3 request input p60: general-pur pose i/o por t (def ault) sin2: ser ial i/f ch.2 data input dcsio0: dcsio por t excl0: 16-bit timer 0 ev ent counter input p61: general-pur pose i/o por t (def ault) sout2: ser ial i/f ch.2 data output dcsio1: dcsio por t excl1: 16-bit timer 1 ev ent counter input p62: general-pur pose i/o por t (def ault) #sclk2: ser ial i/f ch.2 cloc k input/output #adtrg: a/d con ve r ter tr igger input cmu_clk: cmu e xter nal cloc k output p63: general-pur pose i/o por t (def ault) #srd y2: ser ial i/f ch.2 ready input/output wdt_clk: w atchdog timer cloc k output #wdt_nmi: w atchdog timer nmi signal output p64: general-pur pose i/o por t (def ault) #w ait : w ait cycle request input excl2: 16-bit timer 2 ev ent counter input p65: general-pur pose i/o por t (def ault) sdi: spi data input fpd a t8: lcd data p66: general-pur pose i/o por t (def ault) sdo: spi data output fpd a t9: lcd data p67: general-pur pose i/o por t (def ault) spi_clk: spi cloc k fpd a t10: lcd data p70: general-pur pose i/o por t (def ault) ain0: a/d con ve r ter ch.0 input p71: general-pur pose i/o por t (def ault) ain1: a/d con ve r ter ch.1 input p72: general-pur pose i/o por t (def ault) ain2: a/d con ve r ter ch.2 input p73: general-pur pose i/o por t (def ault) ain3: a/d con ve r ter ch.3 input p74: general-pur pose i/o por t (def ault) ain4: a/d con ve r ter ch.4 input excl5: 16-bit timer 5 ev ent counter input p80: general-pur pose i/o por t (def ault) fpframe: lcd frame cloc k output p81: general-pur pose i/o por t (def ault) fpline: lcd line cloc k output p82: general-pur pose i/o por t (def ault) fpshift : lcd shift cloc k output p83: general-pur pose i/o por t (def ault) fpdrd y: lcd drd y/mod signal output tft_ctl1: lcdc tft i/f control signal 1 output bclk: bus cloc k output p84: general-pur pose i/o por t (def ault) dcsio0: dcsio por t fpd a t11: lcd data p85: general-pur pose i/o por t (def ault) dcsio1: dcsio por t p90: general-pur pose i/o por t (def ault) fpd a t0: lcd data p91: general-pur pose i/o por t (def ault) fpd a t1: lcd data p92: general-pur pose i/o por t (def ault) fpd a t2: lcd data p93: general-pur pose i/o por t (def ault) fpd a t3: lcd data p94: general-pur pose i/o por t (def ault) fpd a t4: lcd data qfp 11 77 78 79 80 34 35 36 37 52 51 50 49 48 53 54 55 56 57 58 63 64 65 66 68 pin no. pin name p33 card5 #dmareq3 p60 sin2 dcsio0 excl0 p61 sout2 dcsio1 excl1 p62 #sclk2 #adtrg cmu_clk p63 #srd y2 wdt_clk #wdt_nmi p64 #w ait excl2 p65 sdi fpd at 8 p66 sdo fpd at 9 p67 spi_clk fpd a t10 p70 ain0 p71 ain1 p72 ain2 p73 ain3 p74 ain4 excl5 p80 fpframe p81 fpline p82 fpshift p83 fpdrd y tft_ctl1 bclk p84 dcsio0 fpd a t11 p85 dcsio1 p90 fpd at 0 p91 fpd at 1 p92 fpd at 2 p93 fpd at 3 p94 fpd at 4 pfbga e1 l13 k12 j12 k14 k3 m2 m3 n1 n6 m6 n7 m5 n5 p7 l6 l7 m7 l8 m8 l10 l11 p10 m10 m11
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p95: general-pur pose i/o por t (def ault) fpd a t5: lcd data p96: general-pur pose i/o por t (def ault) fpd a t6: lcd data p97: general-pur pose i/o por t (def ault) fpd a t7: lcd data p a0: extended general-pur pose i/o por t (def ault) tft_ctl0: lcdc tft i/f control signal 0 output p a1: extended general-pur pose i/o por t (def ault) fpd a t8: lcd data tft_ctl0: lcdc tft i/f control signal 0 output p a2: extended general-pur pose i/o por t (def ault) fpd a t9: lcd data tft_ctl1: lcdc tft i/f control signal 1 output p a3: extended general-pur pose i/o por t (def ault) fpd a t10: lcd data tft_ctl2: lcdc tft i/f control signal 2 output card0: card i/f signal 0 output p a4: extended general-pur pose i/o por t (def ault) fpd a t11: lcd data tft_ctl3: lcdc tft i/f control signal 3 output card1: card i/f signal 1 output pb0: extended general-pur pose i/o por t (def ault) fpd a t8: lcd data i2s_sdo: i 2 s send data signal card2: card i/f signal 2 output pb1: extended general-pur pose i/o por t (def ault) fpd a t9: lcd data i2s_ws: i 2 s word select signal card3: card i/f signal 3 output pb2: extended general-pur pose i/o por t (def ault) fpd a t10: lcd data i2s_sck: i 2 s ser ial cloc k signal card4: card i/f signal 4 output pb3: extended general-pur pose i/o por t (def ault) fpd a t11: lcd data i2s_mclk: i 2 s master cloc k signal card5: card i/f signal 5 output qfp 69 70 71 C C C C C C C C C pin no. pin name p95 fpd at 5 p96 fpd at 6 p97 fpd at 7 pa 0 tft_ctl0 pa 1 fpd at 8 tft_ctl0 pa 2 fpd at 9 tft_ctl1 pa 3 fpd a t10 tft_ctl2 card0 pa 4 fpd a t11 tft_ctl3 card1 pb0 fpd at 8 i2s_sdo card2 pb1 fpd at 9 i2s_ws card3 pb2 fpd a t10 i2s_sck card4 pb3 fpd a t11 i2s_mclk card5 pfbga n10 n12 m12 p11 n11 l12 p12 p13 l2 l4 l3 m1 table i.3.2.5 usb interface pin list i/o i /o i /o i pull- up/do wn C C C function usb d+ pin usb d- pin usb vbus pin. allo ws input of 5 v qfp 75 74 76 pin no. pin name usbdp usbdm usbvbus pfbga m14 n14 l14 table i.3.2.6 other pin list i/o i i i /o i/ o (h) i/ o (l) i i i i pull- up/do wn 50k pu 50k pu 50k pu 50k pu 100k pu C C 50k pd 60k pd function initial reset input pin (with noise reduction circuit) nmi request input pin (with noise reduction circuit) dsio: ser ial input/output f or deb ugging (with noise reduction circuit) (def ault) p34: general-pur pose i/o por t dclk: dclk signal output f or deb ugging (def ault) p35: general-pur pose i/o por t dst2: dst2 signal output f or deb ugging (def ault) p36: general-pur pose i/o por t boot mode select signal 1 input boot mode select signal 0 input wa f er le v el bu r n-in test enab le input test -0 input qfp 72 73 31 33 32 46 C C 45 pin no. pin name #reset #nmi dsio p34 dclk p35 dst2 p36 boo t1 boo t0 burnin test0 pfbga n13 m13 k1 l1 k4 l5 k13 m9 m4
i s1c33e08 specifications: pin description i-3-8 epson s1c33e08 technical manual ?1 : these pins can have pull-ups enabled or disabled by setting the pin control registers. ?2 : these pins come with a bus hold latch. ?3 : the input/output direction of the #ce10 pin at initial reset depends on the configuration of the boot[1:0 ] pins. refer to appendix d boot for details. notes : ? the # prefixed to pin names indicates that input/output signals of the pin are active low. ? the pin names listed in boldface denote the default pin (signal) name. ? the i/o listed in boldface and uppercase denote the default input/output direction. ( ) for i/o indicates the following pin states: (h), (l): default output level. this is only indicated for signals whose level is fixed high or low when the chip is initially reset. (pu): the pin is pulled up at initial reset (register control pull- up is enabled). (hi-z): the pin is placed in high impedance state at initial reset (register control pull-up is disabled). ? the input level must be v dd only for the mclki and rtc_clki pins. input levels for other pins should be v ddh (or av dd ) level. ? the pa ? and pb ? port pins are not available in the qfp package. do not set these ports to a condition (input mode and pull-up off) that may place the port into floating status. ? the boot0 pin is not available in the qfp package. the boot0 signal is pulled down to low inside the package.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.3 switching over the multiplexed pin functions i.3.3.1 pin function select bits each pin is assigned one to four functions, as listed in table i. 3.3.1.1. when the chip is powered on or cold-reset, each pin defaults to function 0 except for the p21 /sdclk pin and debug pins. if any pin must be used for other than this default function, select the desired function by writing data to the corresponding pin function select bits. table i.3.3.1.1 list of pin function select bits pin function 0 mclki mclko rtc_clki rtc_clko vcp #reset #nmi boot1 boot0 burnin dsio dclk dst2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0/#bsl a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16/dqml a17/dqmh a18 a19 a20 pin function 1 p34 p35 p36 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 p47 p46 p45 p44 pin function 2 tft_ctl2 fpd a t11 fpd a t10 pin function 3 deb ug function function select bit cfp34[1:0] (d[1:0]/0x3003a7) cfp35[1:0] (d[3:2]/0x3003a7) cfp36[1:0] (d[5:4]/0x3003a7) cfpc0[1:0] (d[1:0]/0x300c24) cfpc1[1:0] (d[3:2]/0x300c24) cfpc2[1:0] (d[5:4]/0x300c24) cfpc3[1:0] (d[7:6]/0x300c24) cfpc4[1:0] (d[1:0]/0x300c25) cfpc5[1:0] (d[3:2]/0x300c25) cfpc6[1:0] (d[5:4]/0x300c25) cfpc7[1:0] (d[7:6]/0x300c25) cfp47[1:0] (d[7:6]/0x3003a9) cfp46[1:0] (d[5:4]/0x3003a9) cfp45[1:0] (d[3:2]/0x3003a9) cfp44[1:0] (d[1:0]/0x3003a9)
i s1c33e08 specifications: pin description i-3-10 epson s1c33e08 technical manual pin function 0 a21 a22 a23 a24 #rd #wrl #wrh/#bsh #ce10 #ce4 #ce5 p52 #ce7 #ce8 #ce9 #ce11 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p73 p74 p80 p81 p82 p83 p84 p85 pin function 1 p43 p42 p41 p40 p57 p50 p51 bclk p53 p54 p55 p56 sin0 sout0 #sclk0 #srd y0 sin1 sout1 #sclk1 #srd y1 tm0 tm1 tm2 tm3 tm4 tm5 dcsio0 dcsio1 sdcke sdclk #sdcs #sdras #sdcas #sd we dqml dqmh card2 card3 card4 card5 sin2 sout2 #sclk2 #srd y2 #w ait sdi sdo spi_clk ain0 ain1 ain2 ain3 ain4 fpframe fpline fpshift fpdrd y dcsio0 dcsio1 pin function 2 fpd at 9 fpd at 8 #sdras #sdcas card0 card1 #ce6 sd a10 card1 card0 #dmaa ck2 #dmaa ck3 #dmaend2 #dmaend3 i2s_sdo i2s_ws i2s_sck i2s_mclk sin0 sout0 #sclk0 #srd y0 sin1 sout1 #sclk1 #srd y1 tft_ctl1 #dmareq0 #dmareq1 #dmareq2 #dmareq3 dcsio0 dcsio1 #adtrg wdt_clk excl2 fpd at 8 fpd at 9 fpd a t10 excl5 tft_ctl1 fpd a t11 pin function 3 excl3 excl4 cmu_clk #dmaend0 #dmaend1 #dmaa ck0 #dmaa ck1 tft_ctl0 tft_ctl3 tft_ctl2 excl0 excl1 cmu_clk #wdt_nmi bclk deb ug function dst0 dst1 dpco function select bit cfp43[1:0] (d[7:6]/0x3003a8) cfp42[1:0] (d[5:4]/0x3003a8) cfp41[1:0] (d[3:2]/0x3003a8) cfp40[1:0] (d[1:0]/0x3003a8) cfp57[1:0] (d[7:6]/0x3003ab) cfp50[1:0] (d[1:0]/0x3003aa) cfp51[1:0] (d[3:2]/0x3003aa) cfp52[1:0] (d[5:4]/0x3003aa) cfp53[1:0] (d[7:6]/0x3003aa) cfp54[1:0] (d[1:0]/0x3003ab) cfp55[1:0] (d[3:2]/0x3003ab) cfp56[1:0] (d[5:4]/0x3003ab) cfp00[1:0] (d[1:0]/0x3003a0) cfp01[1:0] (d[3:2]/0x3003a0) cfp02[1:0] (d[5:4]/0x3003a0) cfp03[1:0] (d[7:6]/0x3003a0) cfp04[1:0] (d[1:0]/0x3003a1) cfp05[1:0] (d[3:2]/0x3003a1) cfp06[1:0] (d[5:4]/0x3003a1) cfp07[1:0] (d[7:6]/0x3003a1) cfp10[1:0] (d[1:0]/0x3003a2) cfp11[1:0] (d[3:2]/0x3003a2) cfp12[1:0] (d[5:4]/0x3003a2) cfp13[1:0] (d[7:6]/0x3003a2) cfp14[1:0] (d[1:0]/0x3003a3) cfp15[1:0] (d[3:2]/0x3003a3) cfp16[1:0] (d[5:4]/0x3003a3) cfp17[1:0] (d[7:6]/0x3003a3) cfp20[1:0] (d[1:0]/0x3003a4) cfp21[1:0] (d[3:2]/0x3003a4) cfp22[1:0] (d[5:4]/0x3003a4) cfp23[1:0] (d[7:6]/0x3003a4) cfp24[1:0] (d[1:0]/0x3003a5) cfp25[1:0] (d[3:2]/0x3003a5) cfp26[1:0] (d[5:4]/0x3003a5) cfp27[1:0] (d[7:6]/0x3003a5) cfp30[1:0] (d[1:0]/0x3003a6) cfp31[1:0] (d[3:2]/0x3003a6) cfp32[1:0] (d[5:4]/0x3003a6) cfp33[1:0] (d[7:6]/0x3003a6) cfp60[1:0] (d[1:0]/0x3003a c) cfp61[1:0] (d[3:2]/0x3003a c) cfp62[1:0] (d[5:4]/0x3003a c) cfp63[1:0] (d[7:6]/0x3003a c) cfp64[1:0] (d[1:0]/0x3003ad) cfp65[1:0] (d[3:2]/0x3003ad) cfp66[1:0] (d[5:4]/0x3003ad) cfp67[1:0] (d[7:6]/0x3003ad) cfp70[1:0] (d[1:0]/0x3003ae) cfp71[1:0] (d[3:2]/0x3003ae) cfp72[1:0] (d[5:4]/0x3003ae) cfp73[1:0] (d[7:6]/0x3003ae) cfp74[1:0] (d[1:0]/0x3003af) cfp80[1:0] (d[1:0]/0x3003b0) cfp81[1:0] (d[3:2]/0x3003b0) cfp82[1:0] (d[5:4]/0x3003b0) cfp83[1:0] (d[7:6]/0x3003b0) cfp84[1:0] (d[1:0]/0x3003b1) cfp85[1:0] (d[3:2]/0x3003b1)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 pin function 0 p90 p91 p92 p93 p94 p95 p96 p97 pa0 pa1 pa2 pa3 pa4 pb0 pb1 pb2 pb3 usbdp usbdm usbvbus test0 pin function 1 fpd at 0 fpd at 1 fpd at 2 fpd at 3 fpd at 4 fpd at 5 fpd at 6 fpd at 7 tft_ctl0 fpd at 8 fpd at 9 fpd a t10 fpd a t11 fpd at 8 fpd at 9 fpd a t10 fpd a t11 pin function 2 tft_ctl0 tft_ctl1 tft_ctl2 tft_ctl3 i2s_sdo i2s_ws i2s_sck i2s_mclk pin function 3 card0 card1 card2 card3 card4 card5 deb ug function function select bit cfp90[1:0] (d[1:0]/0x3003b2) cfp91[1:0] (d[3:2]/0x3003b2) cfp92[1:0] (d[5:4]/0x3003b2) cfp93[1:0] (d[7:6]/0x3003b2) cfp94[1:0] (d[1:0]/0x3003b3) cfp95[1:0] (d[3:2]/0x3003b3) cfp96[1:0] (d[5:4]/0x3003b3) cfp97[1:0] (d[7:6]/0x3003b3) cfp a0[1:0] (d[1:0]/0x300c20) cfp a1[1:0] (d[3:2]/0x300c20) cfp a2[1:0] (d[5:4]/0x300c20) cfp a3[1:0] (d[7:6]/0x300c20) cfp a4[1:0] (d[1:0]/0x300c21) cfpb0[1:0] (d[1:0]/0x300c22) cfpb1[1:0] (d[3:2]/0x300c22) cfpb2[1:0] (d[5:4]/0x300c22) cfpb3[1:0] (d[7:6]/0x300c22) ? the set values 0 to 3 of the pin function select bits correspond to functions 0 to 3 , respectively. ? when trcmux (d0/0x300014 ) = 1 (default), the p15 Cp17 and p34 Cp36 pins are configured as debug-only pins and the function select bits are ineffective. to use the pin function other than debugging, set trcmux (d0/0x300014) to 0 before setting the function select bit. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) ? card0 to card5 are the output pins for card interfaces. the functions of respective pins can be selected according to the card interface used, as listed in table i. 3.3.1.2 . use the card i/f output port configuration register ( 0x300302 ) to select the functions of these pins. for details of the card interfaces and output signals, see section v. 4, card interface (card). table i. 3.3.1.2 relationship between ports and card interface signals pin name card0 card1 card2 card3 card4 card5 function 0 (default) #smrd #smwr #iord #io wr #oe #we function select bit cardio0 (d0/0x300302) cardio1 (d1/0x300302) cardio2 (d2/0x300302) cardio3 (d3/0x300302) cardio4 (d4/0x300302) cardio5 (d5/0x300302) function 1 #cfce1 #cfce2 #smrd #smwr #cfce1 #cfce2 #smrd, #smwr: output pins for smartmedia (nand flash) #cfce 1, #cfce2 : output pins for compactflash #iord, #iowr, #oe, #we: output pins for pc card ? cardio x : card x port function select bit in the card i/f output port configuration register (d x /0x300302)
i s1c33e08 specifications: pin description i-3-12 epson s1c33e08 technical manual i.3.3.2 list of port function select registers table i.3.3.2.1 list of port function select registers address 0x003003a0 0x003003a1 0x003003a2 0x003003a3 0x003003a4 0x003003a5 0x003003a6 0x003003a7 0x003003a8 0x003003a9 0x003003aa 0x003003ab 0x003003ac 0x003003ad 0x003003ae 0x003003af 0x003003b0 0x003003b1 0x003003b2 0x003003b3 0x00300c20 0x00300c21 0x00300c22 0x00300c24 0x00300c25 function selects p00Cp03 port pin functions. selects p 04Cp07 port pin functions. selects p 10Cp13 port pin functions. selects p14Cp17 port pin functions. selects p20Cp23 port pin functions. selects p24Cp27 port pin functions. selects p30Cp33 port pin functions. selects p34Cp36 port pin functions. selects p40Cp43 port pin functions. selects p44Cp47 port pin functions. selects p50Cp53 port pin functions. selects p54Cp57 port pin functions. selects p60Cp63 port pin functions. selects p64Cp67 port pin functions. selects p70Cp73 port pin functions. selects p74 port pin function. selects p80Cp83 port pin functions. selects p84Cp85 port pin functions. selects p90Cp93 port pin functions. selects p94Cp97 port pin functions. selects pa0Cpa3 port pin functions. * selects pa4 port pin function. * selects pb0Cpb3 port pin functions. * selects pc0Cpc3 port pin functions. selects pc4Cpc7 port pin functions. register name p00Cp03 port function select register (pp0_03_cfp) p04Cp07 port function select register (pp0_47_cfp) p10Cp13 port function select register (pp1_03_cfp) p14Cp17 port function select register (pp1_47_cfp) p20Cp23 port function select register (pp2_03_cfp) p24Cp27 port function select register (pp2_47_cfp) p30Cp33 port function select register (pp3_03_cfp) p34Cp36 port function select register (pp3_46_cfp) p40Cp43 port function select register (pp4_03_cfp) p44Cp47 port function select register (pp4_47_cfp) p50Cp53 port function select register (pp5_03_cfp) p54Cp57 port function select register (pp5_47_cfp) p60Cp63 port function select register (pp6_03_cfp) p64Cp67 port function select register (pp6_47_cfp) p70Cp73 port function select register (pp7_03_cfp) p74 port function select register (pp7_4_cfp) p80Cp83 port function select register (pp8_03_cfp) p84Cp85 port function select register (pp8_45_cfp) p90Cp93 port function select register (pp9_03_cfp) p94Cp97 port function select register (pp9_47_cfp) pa0Cpa3 port function select register (ppa_03_cfp) pa4 port function select register (ppa_4_cfp) pb0Cpb3 port function select register (ppb_03_cfp) pc0Cpc3 port function select register (ppc_03_cfp) pc4Cpc7 port function select register (ppc_47_cfp) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 * these ports are not available in the qfp24-144pin model. the following describes each port function select register. the port function select registers are mapped to addresses 0x3003a0 to 0x3003b3 and 0x300c20 to 0x300c25, and can be accessed in units of bytes.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a0: p00Cp03 port function select register (pp0_03_cfp) name address register name bit function setting init. r/w remarks cfp031 cfp030 cfp021 cfp020 cfp011 cfp010 cfp001 cfp000 d7 d6 d5 d4 d3 d2 d1 d0 p03 port extended function p02 port extended function p01 port extended function p00 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a0 (b) p00Cp03 port function select register (pp0_03_cfp) cfp03[1:0] function reserved #dmaend3 #srdy0 p03 cfp02[1:0] function reserved #dmaend2 #sclk0 p02 cfp01[1:0] function reserved #dmaack3 sout0 p01 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp00[1:0] function reserved #dmaack2 sin0 p00 this register selects the functions of ports p 00 to p03. d[7:6] cfp03[1:0]: p03 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaend3 01 (r/w): #srdy0 00 (r/w): p03 (default) d[5:4] cfp02[1:0]: p02 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaend2 01 (r/w): #sclk0 00 (r/w): p02 (default) d[3:2] cfp01[1:0]: p01 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaack3 01 (r/w): sout0 00 (r/w): p01 (default) d[1:0] cfp00[1:0]: p00 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaack2 01 (r/w): sin0 00 (r/w): p00 (default)
i s1c33e08 specifications: pin description i-3-14 epson s1c33e08 technical manual 0x3003a1: p04Cp07 port function select register (pp0_47_cfp) name address register name bit function setting init. r/w remarks cfp071 cfp070 cfp061 cfp060 cfp051 cfp050 cfp041 cfp040 d7 d6 d5 d4 d3 d2 d1 d0 p07 port extended function p06 port extended function p05 port extended function p04 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a1 (b) p04Cp07 port function select register (pp0_47_cfp) cfp07[1:0] function reserved i2s_mclk #srdy1 p07 cfp06[1:0] function reserved i2s_sck #sclk1 p06 cfp05[1:0] function reserved i2s_ws sout1 p05 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp04[1:0] function reserved i2s_sdo sin1 p04 this register selects the functions of ports p 04 to p07. d[7:6] cfp07[1:0]: p07 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_mclk 01 (r/w): #srdy1 00 (r/w): p07 (default) d[5:4] cfp06[1:0]: p06 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_sck 01 (r/w): #sclk1 00 (r/w): p06 (default) d[3:2] cfp05[1:0]: p05 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_ws 01 (r/w): sout1 00 (r/w): p05 (default) d[1:0] cfp04[1:0]: p04 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_sdo 01 (r/w): sin1 00 (r/w): p04 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-15 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a2: p10Cp13 port function select register (pp1_03_cfp) name address register name bit function setting init. r/w remarks cfp131 cfp130 cfp121 cfp120 cfp111 cfp110 cfp101 cfp100 d7 d6 d5 d4 d3 d2 d1 d0 p13 port extended function p12 port extended function p11 port extended function p10 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a2 (b) p10Cp13 port function select register (pp1_03_cfp) cfp13[1:0] function #dmaack1 #srdy0 tm3 p13 cfp12[1:0] function #dmaack0 #sclk0 tm2 p12 cfp11[1:0] function #dmaend1 sout0 tm1 p11 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp10[1:0] function #dmaend0 sin0 tm0 p10 this register selects the functions of ports p 10 to p13. d[7:6] cfp13[1:0]: p13 port extended function select bits 11 (r/w): #dmaack1 10 (r/w): #srdy0 01 (r/w): tm3 00 (r/w): p13 (default) d[5:4] cfp12[1:0]: p12 port extended function select bits 11 (r/w): #dmaack0 10 (r/w): #sclk0 01 (r/w): tm2 00 (r/w): p12 (default) d[3:2] cfp11[1:0]: p11 port extended function select bits 11 (r/w): #dmaend1 10 (r/w): sout0 01 (r/w): tm1 00 (r/w): p11 (default) d[1:0] cfp10[1:0]: p10 port extended function select bits 11 (r/w): #dmaend0 10 (r/w): sin0 01 (r/w): tm0 00 (r/w): p10 (default)
i s1c33e08 specifications: pin description i-3-16 epson s1c33e08 technical manual 0x3003a3: p14Cp17 port function select register (pp1_47_cfp) name address register name bit function setting init. r/w remarks cfp171 cfp170 cfp161 cfp160 cfp151 cfp150 cfp141 cfp140 d7 d6 d5 d4 d3 d2 d1 d0 p17 port extended function p16 port extended function p15 port extended function p14 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a3 (b) p14Cp17 port function select register (pp1_47_cfp) cfp17[1:0] function tft_ctl2 #srdy1 dcsio1 p17 cfp16[1:0] function tft_ctl3 #sclk1 dcsio0 p16 cfp15[1:0] function tft_ctl0 sout1 tm5 p15 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp14[1:0] function reserved sin1 tm4 p14 this register selects the functions of ports p 14 to p17. d[7:6] cfp17[1:0]: p17 port extended function select bits 11 (r/w): tft_ctl2 10 (r/w): #srdy1 01 (r/w): dcsio1 00 (r/w): p17 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p17 is configured as the dpco pin for debugging. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) d[5:4] cfp16[1:0]: p16 port extended function select bits 11 (r/w): tft_ctl3 10 (r/w): #sclk1 01 (r/w): dcsio0 00 (r/w): p16 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p16 is configured as the dst 1 pin for debugging. d[3:2] cfp15[1:0]: p15 port extended function select bits 11 (r/w): tft_ctl0 10 (r/w): sout1 01 (r/w): tm5 00 (r/w): p15 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p15 is configured as the dst 0 pin for debugging. d[1:0] cfp14[1:0]: p14 port extended function select bits 11 (r/w): reserved 10 (r/w): sin1 01 (r/w): tm4 00 (r/w): p14 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-17 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a4: p20Cp23 port function select register (pp2_03_cfp) name address register name bit function setting init. r/w remarks cfp231 cfp230 cfp221 cfp220 cfp211 cfp210 cfp201 cfp200 d7 d6 d5 d4 d3 d2 d1 d0 p23 port extended function p22 port extended function p21 port extended function p20 port extended function 0 0 0 0 0 1 0 0 r/w r/w r/w r/w 003003a4 (b) p20Cp23 port function select register (pp2_03_cfp) cfp23[1:0] function reserved tft_ctl1 #sdras p23 cfp22[1:0] function reserved #sdcs p22 cfp21[1:0] function reserved sdclk p21 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp20[1:0] function reserved sdcke p20 this register selects the functions of ports p 20 to p23. d[7:6] cfp23[1:0]: p23 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl1 01 (r/w): #sdras 00 (r/w): p23 (default) d[5:4] cfp22[1:0]: p22 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdcs 00 (r/w): p22 (default) d[3:2] cfp21[1:0]: p21 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): sdclk (default) 00 (r/w): p21 d[1:0] cfp20[1:0]: p20 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): sdcke 00 (r/w): p20 (default)
i s1c33e08 specifications: pin description i-3-18 epson s1c33e08 technical manual 0x3003a5: p24Cp27 port function select register (pp2_47_cfp) name address register name bit function setting init. r/w remarks cfp271 cfp270 cfp261 cfp260 cfp251 cfp250 cfp241 cfp240 d7 d6 d5 d4 d3 d2 d1 d0 p27 port extended function p26 port extended function p25 port extended function p24 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a5 (b) p24Cp27 port function select register (pp2_47_cfp) cfp27[1:0] function reserved dqmh p27 cfp26[1:0] function reserved dqml p26 cfp25[1:0] function reserved #sdwe p25 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp24[1:0] function reserved #sdcas p24 this register selects the functions of ports p 24 to p27. d[7:6] cfp27[1:0]: p27 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dqmh 00 (r/w): p27 (default) d[5:4] cfp26[1:0]: p26 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dqml 00 (r/w): p26 (default) d[3:2] cfp25[1:0]: p25 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdwe 00 (r/w): p25 (default) d[1:0] cfp24[1:0]: p24 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdcas 00 (r/w): p24 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-19 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a6: p30Cp33 port function select register (pp3_03_cfp) name address register name bit function setting init. r/w remarks cfp331 cfp330 cfp321 cfp320 cfp311 cfp310 cfp301 cfp300 d7 d6 d5 d4 d3 d2 d1 d0 p33 port extended function p32 port extended function p31 port extended function p30 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a6 (b) p30Cp33 port function select register (pp3_03_cfp) cfp33[1:0] function reserved #dmareq3 card5 p33 cfp32[1:0] function reserved #dmareq2 card4 p32 cfp31[1:0] function reserved #dmareq1 card3 p31 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp30[1:0] function reserved #dmareq0 card2 p30 this register selects the functions of ports p 30 to p33. d[7:6] cfp33[1:0]: p33 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq3 01 (r/w): card5 00 (r/w): p33 (default) d[5:4] cfp32[1:0]: p32 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq2 01 (r/w): card4 00 (r/w): p32 (default) d[3:2] cfp31[1:0]: p31 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq1 01 (r/w): card3 00 (r/w): p31 (default) d[1:0] cfp30[1:0]: p30 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq0 01 (r/w): card2 00 (r/w): p30 (default)
i s1c33e08 specifications: pin description i-3-20 epson s1c33e08 technical manual 0x3003a7: p34Cp36 port function select register (pp3_46_cfp) name address register name bit function setting init. r/w remarks C cfp361 cfp360 cfp351 cfp350 cfp341 cfp340 d7C6 d5 d4 d3 d2 d1 d0 reserved p36 port extended function p35 port extended function p34 port extended function C 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a7 (b) p34Cp36 port function select register (pp3_46_cfp) cfp36[1:0] function C reserved p36 dst2 cfp35[1:0] function reserved p35 dclk 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp34[1:0] function reserved p34 dsio this register selects the functions of ports p 34 to p36. d[7:6] reserved d[5:4] cfp36[1:0]: p36 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p36 00 (r/w): dst2 (default) to use p 36 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp36[1:0] set to 01. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) d[3:2] cfp35[1:0]: p35 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p35 00 (r/w): dclk (default) to use p 35 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp35[1:0] set to 01. d[1:0] cfp34[1:0]: p34 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p34 00 (r/w): dsio (default) to use p 34 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp34[1:0] set to 01.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-21 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a8: p40Cp43 port function select register (pp4_03_cfp) name address register name bit function setting init. r/w remarks cfp431 cfp430 cfp421 cfp420 cfp411 cfp410 cfp401 cfp400 d7 d6 d5 d4 d3 d2 d1 d0 p43 port extended function p42 port extended function p41 port extended function p40 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a8 (b) p40Cp43 port function select register (pp4_03_cfp) cfp43[1:0] function reserved fpdat9 p43 a21 cfp42[1:0] function reserved fpdat8 p42 a22 cfp41[1:0] function excl3 #sdras p41 a23 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp40[1:0] function excl4 #sdcas p40 a24 this register selects the functions of ports p 40 to p43. d[7:6] cfp43[1:0]: p43 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat9 01 (r/w): p43 00 (r/w): a21 (default) d[5:4] cfp42[1:0]: p42 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat8 01 (r/w): p42 00 (r/w): a22 (default) d[3:2] cfp41[1:0]: p41 port extended function select bits 11 (r/w): excl3 10 (r/w): #sdras 01 (r/w): p41 00 (r/w): a23 (default) d[1:0] cfp40[1:0]: p40 port extended function select bits 11 (r/w): excl4 10 (r/w): #sdcas 01 (r/w): p40 00 (r/w): a24 (default)
i s1c33e08 specifications: pin description i-3-22 epson s1c33e08 technical manual 0x3003a9: p44Cp47 port function select register (pp4_47_cfp) name address register name bit function setting init. r/w remarks cfp471 cfp470 cfp461 cfp460 cfp451 cfp450 cfp441 cfp440 d7 d6 d5 d4 d3 d2 d1 d0 p47 port extended function p46 port extended function p45 port extended function p44 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a9 (b) p44Cp47 port function select register (pp4_47_cfp) cfp47[1:0] function reserved p47 a11 cfp46[1:0] function reserved tft_ctl2 p46 a18 cfp45[1:0] function reserved fpdat11 p45 a19 11 10 01 00 11 10 01 00 11 10 01 00 1 ? 01 00 cfp44[1:0] function reserved fpdat10 p44 a20 this register selects the functions of ports p 44 to p47. d[7:6] cfp47[1:0]: p47 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p47 00 (r/w): a11 (default) d[5:4] cfp46[1:0]: p46 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl2 01 (r/w): p46 00 (r/w): a18 (default) d[3:2] cfp45[1:0]: p45 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat11 01 (r/w): p45 00 (r/w): a19 (default) d[1:0] cfp44[1:0]: p44 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat10 01 (r/w): p44 00 (r/w): a20 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-23 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003aa: p50Cp53 port function select register (pp5_03_cfp) name address register name bit function setting init. r/w remarks cfp531 cfp530 cfp521 cfp520 cfp511 cfp510 cfp501 cfp500 d7 d6 d5 d4 d3 d2 d1 d0 p53 port extended function p52 port extended function p51 port extended function p50 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003aa (b) p50Cp53 port function select register (pp5_03_cfp) cfp53[1:0] function reserved sda10 p53 #ce7 cfp52[1:0] function cmu_clk #ce6 bclk p52 cfp51[1:0] function reserved card1 p51 #ce5 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp50[1:0] function reserved card0 p50 #ce4 this register selects the functions of ports p 50 to p53. d[7:6] cfp53[1:0]: p53 port extended function select bits 11 (r/w): reserved 10 (r/w): sda10 01 (r/w): p53 00 (r/w): #ce7 (default) d[5:4] cfp52[1:0]: p52 port extended function select bits 11 (r/w): cmu_clk 10 (r/w): #ce6 01 (r/w): bclk 00 (r/w): p52 (default) d[3:2] cfp51[1:0]: p51 port extended function select bits 11 (r/w): reserved 10 (r/w): card1 01 (r/w): p51 00 (r/w): #ce5 (default) d[1:0] cfp50[1:0]: p50 port extended function select bits 11 (r/w): reserved 10 (r/w): card0 01 (r/w): p50 00 (r/w): #ce4 (default)
i s1c33e08 specifications: pin description i-3-24 epson s1c33e08 technical manual 0x3003ab: p54Cp57 port function select register (pp5_47_cfp) name address register name bit function setting init. r/w remarks cfp571 cfp570 cfp561 cfp560 cfp551 cfp550 cfp541 cfp540 d7 d6 d5 d4 d3 d2 d1 d0 p57 port extended function p56 port extended function p55 port extended function p54 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ab (b) p54Cp57 port function select register (pp5_47_cfp) cfp57[1:0] function reserved p57 #ce10 cfp56[1:0] function reserved p56 #ce11 cfp55[1:0] function reserved card0 p55 #ce9 11 10 01 00 11 10 01 00 1 ? 01 00 1 ? 01 00 cfp54[1:0] function reserved card1 p54 #ce8 this register selects the functions of ports p 54 to p57. d[7:6] cfp57[1:0]: p57 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p57 00 (r/w): #ce10 (default) d[5:4] cfp56[1:0]: p56 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p56 00 (r/w): #ce11 (default) d[3:2] cfp55[1:0]: p55 port extended function select bits 11 (r/w): reserved 10 (r/w): card0 01 (r/w): p55 00 (r/w): #ce9 (default) d[1:0] cfp54[1:0]: p54 port extended function select bits 11 (r/w): reserved 10 (r/w): card1 01 (r/w): p54 00 (r/w): #ce8 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-25 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003ac: p60Cp63 port function select register (pp6_03_cfp) name address register name bit function setting init. r/w remarks cfp631 cfp630 cfp621 cfp620 cfp611 cfp610 cfp601 cfp600 d7 d6 d5 d4 d3 d2 d1 d0 p63 port extended function p62 port extended function p61 port extended function p60 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ac (b) p60Cp63 port function select register (pp6_03_cfp) cfp63[1:0] function #wdt_nmi wdt_clk #srdy2 p63 cfp62[1:0] function cmu_clk #adtrg #sclk2 p62 cfp61[1:0] function excl1 dcsio1 sout2 p61 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp60[1:0] function excl0 dcsio0 sin2 p60 this register selects the functions of ports p 60 to p63. d[7:6] cfp63[1:0]: p63 port extended function select bits 11 (r/w): #wdt_nmi 10 (r/w): wdt_clk 01 (r/w): #srdy2 00 (r/w): p63 (default) d[5:4] cfp62[1:0]: p62 port extended function select bits 11 (r/w): cmu_clk 10 (r/w): #adtrg 01 (r/w): #sclk2 00 (r/w): p62 (default) d[3:2] cfp61[1:0]: p61 port extended function select bits 11 (r/w): excl1 10 (r/w): dcsio1 01 (r/w): sout2 00 (r/w): p61 (default) d[1:0] cfp60[1:0]: p60 port extended function select bits 11 (r/w): excl0 10 (r/w): dcsio0 01 (r/w): sin2 00 (r/w): p60 (default)
i s1c33e08 specifications: pin description i-3-26 epson s1c33e08 technical manual 0x3003ad: p64Cp67 port function select register (pp6_47_cfp) name address register name bit function setting init. r/w remarks cfp671 cfp670 cfp661 cfp660 cfp651 cfp650 cfp641 cfp640 d7 d6 d5 d4 d3 d2 d1 d0 p67 port extended function p66 port extended function p65 port extended function p64 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ad (b) p64Cp67 port function select register (pp6_47_cfp) cfp67[1:0] function reserved fpdat10 spi_clk p67 cfp66[1:0] function reserved fpdat9 sdo p66 cfp65[1:0] function reserved fpdat8 sdi p65 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp64[1:0] function reserved excl2 #wait p64 this register selects the functions of ports p 64 to p67. d[7:6] cfp67[1:0]: p67 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat10 01 (r/w): spi_clk 00 (r/w): p67 (default) d[5:4] cfp66[1:0]: p66 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat9 01 (r/w): sdo 00 (r/w): p66 (default) d[3:2] cfp65[1:0]: p65 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat8 01 (r/w): sdi 00 (r/w): p65 (default) d[1:0] cfp64[1:0]: p64 port extended function select bits 11 (r/w): reserved 10 (r/w): excl2 01 (r/w): #wait 00 (r/w): p64 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-27 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003ae: p70Cp73 port function select register (pp7_03_cfp) name address register name bit function setting init. r/w remarks cfp731 cfp730 cfp721 cfp720 cfp711 cfp710 cfp701 cfp700 d7 d6 d5 d4 d3 d2 d1 d0 p73 port extended function p72 port extended function p71 port extended function p70 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ae (b) p70Cp73 port function select register (pp7_03_cfp) cfp73[1:0] function reserved ain3 p73 cfp72[1:0] function reserved ain2 p72 cfp71[1:0] function reserved ain1 p71 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp70[1:0] function reserved ain0 p70 this register selects the functions of ports p 70 to p73. d[7:6] cfp73[1:0]: p73 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain3 00 (r/w): p73 (default) d[5:4] cfp72[1:0]: p72 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain2 00 (r/w): p72 (default) d[3:2] cfp71[1:0]: p71 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain1 00 (r/w): p71 (default) d[1:0] cfp70[1:0]: p70 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain0 00 (r/w): p70 (default)
i s1c33e08 specifications: pin description i-3-28 epson s1c33e08 technical manual 0x3003af: p74 port function select register (pp7_4_cfp) name address register name bit function setting init. r/w remarks C cfp741 cfp740 d7C2 d1 d0 reserved p74 port extended function C 0 0 C r/w 0 when being read. 003003af (b) p74 port function select register (pp7_4_cfp) cfp74[1:0] function reserved excl5 ain4 p74 C 11 10 01 00 this register selects the function of port p 74. d[7:2] reserved d[1:0] cfp74[1:0]: p74 port extended function select bits 11 (r/w): reserved 10 (r/w): excl5 01 (r/w): ain4 00 (r/w): p74 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-29 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003b0: p80Cp83 port function select register (pp8_03_cfp) name address register name bit function setting init. r/w remarks cfp831 cfp830 cfp821 cfp820 cfp811 cfp810 cfp801 cfp800 d7 d6 d5 d4 d3 d2 d1 d0 p83 port extended function p82 port extended function p81 port extended function p80 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b0 (b) p80Cp83 port function select register (pp8_03_cfp) cfp83[1:0] function bclk tft_ctl1 fpdrdy p83 cfp82[1:0] function reserved fpshift p82 cfp81[1:0] function reserved fpline p81 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp80[1:0] function reserved fpframe p80 this register selects the functions of ports p 80 to p83. d[7:6] cfp83[1:0]: p83 port extended function select bits 11 (r/w): bclk 10 (r/w): tft_ctl1 01 (r/w): fpdrdy 00 (r/w): p83 (default) d[5:4] cfp82[1:0]: p82 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpshift 00 (r/w): p82 (default) d[3:2] cfp81[1:0]: p81 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpline 00 (r/w): p81 (default) d[1:0] cfp80[1:0]: p80 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpframe 00 (r/w): p80 (default)
i s1c33e08 specifications: pin description i-3-30 epson s1c33e08 technical manual 0x3003b1: p84Cp85 port function select register (pp8_45_cfp) name address register name bit function setting init. r/w remarks C cfp851 cfp850 cfp841 cfp840 d7C4 d3 d2 d1 d0 reserved p85 port extended function p84 port extended function C 0 0 0 0 C r/w r/w 0 when being read. 003003b1 (b) p84Cp85 port function select register (pp8_45_cfp) cfp85[1:0] function C reserved dcsio1 p85 cfp84[1:0] function reserved fpdat11 dcsio0 p84 11 10 01 00 1 ? 01 00 this register selects the functions of ports p 84 to p85. d[7:4] reserved d[3:2] cfp85[1:0]: p85 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dcsio1 00 (r/w): p85 (default) d[1:0] cfp84[1:0]: p84 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat11 01 (r/w): dcsio0 00 (r/w): p84 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-31 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003b2: p90Cp93 port function select register (pp9_03_cfp) name address register name bit function setting init. r/w remarks cfp931 cfp930 cfp921 cfp920 cfp911 cfp910 cfp901 cfp900 d7 d6 d5 d4 d3 d2 d1 d0 p93 port extended function p92 port extended function p91 port extended function p90 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b2 (b) p90Cp93 port function select register (pp9_03_cfp) cfp93[1:0] function reserved fpdat3 p93 cfp92[1:0] function reserved fpdat2 p92 cfp91[1:0] function reserved fpdat1 p91 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp90[1:0] function reserved fpdat0 p90 this register selects the functions of ports p 90 to p93. d[7:6] cfp93[1:0]: p93 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat3 00 (r/w): p93 (default) d[5:4] cfp92[1:0]: p92 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat2 00 (r/w): p92 (default) d[3:2] cfp91[1:0]: p91 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat1 00 (r/w): p91 (default) d[1:0] cfp90[1:0]: p90 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat0 00 (r/w): p90 (default)
i s1c33e08 specifications: pin description i-3-32 epson s1c33e08 technical manual 0x3003b3: p94Cp97 port function select register (pp9_47_cfp) name address register name bit function setting init. r/w remarks cfp971 cfp970 cfp961 cfp960 cfp951 cfp950 cfp941 cfp940 d7 d6 d5 d4 d3 d2 d1 d0 p97 port extended function p96 port extended function p95 port extended function p94 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b3 (b) p94Cp97 port function select register (pp9_47_cfp) cfp97[1:0] function reserved fpdat7 p97 cfp96[1:0] function reserved fpdat6 p96 cfp95[1:0] function reserved fpdat5 p95 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp94[1:0] function reserved fpdat4 p94 this register selects the functions of ports p 94 to p97. d[7:6] cfp97[1:0]: p97 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat7 00 (r/w): p97 (default) d[5:4] cfp96[1:0]: p96 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat6 00 (r/w): p96 (default) d[3:2] cfp95[1:0]: p95 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat5 00 (r/w): p95 (default) d[1:0] cfp94[1:0]: p94 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat4 00 (r/w): p94 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-33 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c20: pa0Cpa3 port function select register (ppa_03_cfp) name address register name bit function setting init. r/w remarks cfpa31 cfpa30 cfpa21 cfpa20 cfpa11 cfpa10 cfpa01 cfpa00 d7 d6 d5 d4 d3 d2 d1 d0 pa3 port extended function pa2 port extended function pa1 port extended function pa0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c20 (b) pa0Cpa3 port function select register (ppa_03_cfp) cfpa3[1:0] function card0 tft_ctl2 fpdat10 pa3 cfpa2[1:0] function reserved tft_ctl1 fpdat9 pa2 cfpa1[1:0] function reserved tft_ctl0 fpdat8 pa1 1 ? 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpa0[1:0] function reserved tft_ctl0 pa0 note : the pa0 to pa3 ports are not available in the qfp24-144pin package model. this register selects the functions of ports pa 0 to pa3. d[7:6] cfpa3[1:0]: pa3 port extended function select bits 11 (r/w): card0 10 (r/w): tft_ctl2 01 (r/w): fpdat10 00 (r/w): pa3 (default) d[5:4] cfpa2[1:0]: pa2 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl1 01 (r/w): fpdat9 00 (r/w): pa2 (default) d[3:2] cfpa1[1:0]: pa1 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl0 01 (r/w): fpdat8 00 (r/w): pa1 (default) d[1:0] cfpa0[1:0]: pa0 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): tft_ctl0 00 (r/w): pa0 (default)
i s1c33e08 specifications: pin description i-3-34 epson s1c33e08 technical manual 0x300c21: pa4 port function select register (ppa_4_cfp) name address register name bit function setting init. r/w remarks C cfpa41 cfpa40 d7C2 d1 d0 reserved pa4 port extended function C 0 0 C r/w 0 when being read. 00300c21 (b) pa4 port function select register (ppa_4_cfp) cfpa4[1:0] function card1 tft_ctl3 fpdat11 pa4 11 10 01 00 function C note : the pa4 port is not available in the qfp24-144pin package model. this register selects the function of port pa 4. d[7:2] reserved d[1:0] cfpa4[1:0]: pa4 port extended function select bits 11 (r/w): card1 10 (r/w): tft_ctl3 01 (r/w): fpdat11 00 (r/w): pa4 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-35 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c22: pb0Cpb3 port function select register (ppb_03_cfp) name address register name bit function setting init. r/w remarks cfpb31 cfpb30 cfpb21 cfpb20 cfpb11 cfpb10 cfpb01 cfpb00 d7 d6 d5 d4 d3 d2 d1 d0 pb3 port extended function pb2 port extended function pb1 port extended function pb0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c22 (b) pb0Cpb3 port function select register (ppb_03_cfp) cfpb3[1:0] function card5 i2s_mclk fpdat11 pb3 cfpb2[1:0] function card4 i2s_sck fpdat10 pb2 cfpb1[1:0] function card3 i2s_ws fpdat9 pb1 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpb0[1:0] function card2 i2s_sdo fpdat8 pb0 note : the pb0 to pb3 ports are not available in the qfp24-144pin package model. this register selects the functions of ports pb 0 to pb3. d[7:6] cfpb3[1:0]: pb3 port extended function select bits 11 (r/w): card5 10 (r/w): i2s_mclk 01 (r/w): fpdat11 00 (r/w): pb3 (default) d[5:4] cfpb2[1:0]: pb2 port extended function select bits 11 (r/w): card4 10 (r/w): i2s_sck 01 (r/w): fpdat10 00 (r/w): pb2 (default) d[3:2] cfpb1[1:0]: pb1 port extended function select bits 11 (r/w): card3 10 (r/w): i2s_ws 01 (r/w): fpdat9 00 (r/w): pb1 (default) d[1:0] cfpb0[1:0]: pb0 port extended function select bits 11 (r/w): card2 10 (r/w): i2s_sdo 01 (r/w): fpdat8 00 (r/w): pb0 (default)
i s1c33e08 specifications: pin description i-3-36 epson s1c33e08 technical manual 0x300c24: pc0Cpc3 port function select register (ppc_03_cfp) name address register name bit function setting init. r/w remarks cfpc31 cfpc30 cfpc21 cfpc20 cfpc11 cfpc10 cfpc01 cfpc00 d7 d6 d5 d4 d3 d2 d1 d0 pc3 port extended function pc2 port extended function pc1 port extended function pc0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c24 (b) pc0Cpc3 port function select register (ppc_03_cfp) cfpc3[1:0] function reserved pc3 d11 cfpc2[1:0] function reserved pc2 d10 cfpc1[1:0] function reserved pc1 d9 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc0[1:0] function reserved pc0 d8 this register selects the functions of ports pc 0 to pc3. d[7:6] cfpc3[1:0]: pc3 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc3 00 (r/w): d11 (default) d[5:4] cfpc2[1:0]: pc2 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc2 00 (r/w): d10 (default) d[3:2] cfpc1[1:0]: pc1 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc1 00 (r/w): d9 (default) d[1:0] cfpc0[1:0]: pc0 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc0 00 (r/w): d8 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-37 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c25: pc4Cpc7 port function select register (ppc_47_cfp) name address register name bit function setting init. r/w remarks cfpc71 cfpc70 cfpc61 cfpc60 cfpc51 cfpc50 cfpc41 cfpc40 d7 d6 d5 d4 d3 d2 d1 d0 pc7 port extended function pc6 port extended function pc5 port extended function pc4 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c25 (b) pc4Cpc7 port function select register (ppc_47_cfp) cfpc7[1:0] function reserved pc7 d15 cfpc6[1:0] function reserved pc6 d14 cfpc5[1:0] function reserved pc5 d13 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc4[1:0] function reserved pc4 d12 this register selects the functions of ports pc 4 to pc7. d[7:6] cfpc7[1:0]: pc7 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc7 00 (r/w): d15 (default) d[5:4] cfpc6[1:0]: pc6 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc6 00 (r/w): d14 (default) d[3:2] cfpc5[1:0]: pc5 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc5 00 (r/w): d13 (default) d[1:0] cfpc4[1:0]: pc4 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc4 00 (r/w): d12 (default)
i s1c33e08 specifications: pin description i-3-38 epson s1c33e08 technical manual i.3.4 input/output cells and input/output characteristics table i.3.4.1 pin characteristics i/o cell name lliny llo ty lliny llo ty llo ty hibhp1ty hibhp1ty hibasp2ty hibhp1ty hibhy hbbh2bp1ty hbbh2bp1ty hbbh2bp2ty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty input le vel tr ansparent C tr ansparent C C schmitt schmitt l vcmos schmitt schmitt schmitt schmitt schmitt l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt i oh /i ol C C C C C C C C C C 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 2 ma 2 ma 2 ma pull-up/do wn C C C C C 50 k ? up 50 k ? up 100 k ? up 50 k ? up 50 k ? do wn 50 k ? up 50 k ? up 100 k ? up bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up i/o i o i o o i i i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o po wer sour ce v dd v dd v dd v dd pl v dd v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 2 note 2 note 2 note 2 note 4 note 5 note 5 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 signal name mclki mclko rtc_clki rtc_clko vcp #reset #nmi boot1 boot0 burnin dsio (p34) dclk (p35) dst2 (p36) d0 d1 d2 d3 d4 d5 d6 d7 d8 (pc0) d9 (pc1) d10 (pc2) d11 (pc3) d12 (pc4) d13 (pc5) d14 (pc6) d15 (pc7) a0/#bsl a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 (p47) a12 a13 a14 a15 a16/dqml a17/dqmh a18 (p46/tft_ctl2) a19 (p45/fpdat11) a20 (p44/fpdat10) a21 (p43/fpdat9) a22 (p42/fpdat8) a23 (p41/#sdras/excl3) a24 (p40/#sdcas/excl4) #rd #wrl #wrh/#bsh #ce10 (p57) #ce4 (p50/card0) #ce5 (p51/card1)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-39 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i/o cell name hbbh1bp2ty hbbh2bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hibasp2ty hibasp2ty hibasp2ty hibasp2ty hibasp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty input le vel schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt l vcmos l vcmos l vcmos l vcmos l vcmos schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt i oh /i ol 2 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma C C C C C 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma pull-up/do wn 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o po wer sour ce v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh av dd av dd av dd av dd av dd v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1, 3 note 1, 3 note 1, 3 note 1, 3 note 1, 3 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 signal name p52 (bclk/#ce6/cmu_clk) #ce7 (p53/sda10) #ce8 (p54/card1) #ce9 (p55/card0) #ce11 (p56) p00 (sin0/#dmaack2) p01 (sout0/#dmaack3) p02 (#sclk0/#dmaend2) p03 (#srdy0/#dmaend3) p04 (sin1/i2s_sdo) p05 (sout1/i2s_ws) p06 (#sclk1/i2s_sck) p07 (#srdy1/i2s_mclk) p10 (tm0/sin0/#dmaend0) p11 (tm1/sout0/#dmaend1) p12 (tm2/#sclk0/#dmaack0) p13 (tm3/#srdy0/#dmaack1) p14 (tm4/sin1) dst0 (p15/tm5/sout1/tft_ctl0) dst1 (p16/dcsio0/#sclk1/tft_ctl3) dpco (p17/dcsio1/#srdy1/tft_ctl2) p20 (sdcke) sdclk (p21) p22 (#sdcs) p23 (#sdras/tft_ctl1) p24 (#sdcas) p25 (#sdwe) p26 (dqml) p27 (dqmh) p30 (card2/#dmareq0) p31 (card3/#dmareq1) p32 (card4/#dmareq2) p33 (card5/#dmareq3) p60 (sin2/dcsio0/excl0) p61 (sout2/dcsio1/excl1) p62 (#sclk2/#adtrg/cmu_clk) p63 (#srdy2/wdt_clk/#wdt_nmi) p64 (#wait/excl2) p65 (sdi/fpdat8) p66 (sdo/fpdat9) p67 (spi_clk/fpdat10) p70 (ain0) p71 (ain1) p72 (ain2) p73 (ain3) p74 (ain4/excl5) p80 (fpframe) p81 (fpline) p82 (fpshift) p83 (fpdrdy/tft_ctl1/bclk) p84 (dcsio0/fpdat11) p85 (dcsio1) p90 (fpdat0) p91 (fpdat1) p92 (fpdat2) p93 (fpdat3) p94 (fpdat4) p95 (fpdat5) p96 (fpdat6) p97 (fpdat7)
i s1c33e08 specifications: pin description i-3-40 epson s1c33e08 technical manual i/o cell name hbbh1bp2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty C C C litst1y input le vel schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt C C C l vcmos i oh /i ol 2 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma C C C C pull-up/do wn 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up C C C 60 k ? do wn i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i po wer sour ce v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 signal name pa0 (tft_ctl0) pa1 (fpdat8/tft_ctl0) pa2 (fpdat9/tft_ctl1) pa3 (fpdat10/tft_ctl2/card0) pa4 (fpdat11/tft_ctl3/card1) pb0 (fpdat8/i2s_sdo/card2) pb1 (fpdat9/i2s_ws/card3) pb2 (fpdat10/i2s_sck/card4) pb3 (fpdat11/i2s_mclk/card5) usbdp usbdm usbvbus test0 notes : 1 pull-ups can be enabled or disabled by setting the pin control registers. 2 this pin must be used in input voltage range 0 v vin v dd . 3 this pin must be used in input voltage range 0 v vin av dd . 4 this pin must be used in input voltage range 0 v vin plv dd . 5 these pins are not available in the qfp24-144 pin package model.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-41 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5 package i.3.5.1 qfp24-144 pin package 16 0.1 18 0.4 16 0.1 18 0.4 37 72 1 3 6 108 73 144 109 index 1.0 0.1 0.1 1.2 max 0.16 0.4 +0.10 C0.05 1 0.5 0.2 0 8 0.125 +0.05 C0.025 figure i.3.5.1.1 qfp24-144 pin package dimensions
i s1c33e08 specifications: pin description i-3-42 epson s1c33e08 technical manual pin 1 0 8 f 0 0 a 3 e 3 3 c 1 s f p a n a j (1) y x pkg center line x' y' (2) (15) 0.8 6.0 0.7 0.25 0.8 0.4 0.25 (16) (17) (18) 6.7 1.2 0.8 1.2 0.8 1.2 0.8 1.5 (mm) 6.7 (19) (20) (22) (23) (24) (25) (27) (28) (3) (4) (5) (6) (7) (9) (10) (11) (12) (13) (14) (21) (26) pkg center line (8) figure i.3.5.1.2 qfp24-144 pin package marking
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-43 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5.2 pfbga-180 pin package top view bottom view a1 corner a1 corner index d e a a 1 e z d s d s s y p n m l k j h g f e d c b a symbol d e a a 1 e b x y s d s e z d z e min 11.8 11.8 0.25 0.38 dimension in millimeters nom 12.0 12.0 0.30 0.80 0.43 0.40 0.40 0.80 0.80 max 12.2 12.2 1.20 0.35 0.48 0.08 0.10 b m e z e s e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 figure i.3.5.2.1 pfbga-180 pin package dimensions
i s1c33e08 specifications: pin description i-3-44 epson s1c33e08 technical manual 3 3 e 0 8 0 0 a * c f j a p a n (1 ) y x pkg center lin e x' y' (2 ) (12 ) ( 13) (14) (15) (16) (17 ) (21 ) (22) (23) (24) (25 ) (18) (19) (20) (3 ) (4) (5 ) (6) (7 ) (8) (9 ) (10) (11 ) 3. 1 3. 4 3. 4 3.4 3.4 0. 1 0. 2 0. 5 0. 1 0. 9 0.5 0. 9 0.5 0. 9 0.5 1. 5 1. 5 (mm) pkg center lin e 0. 6 figure i.3.5.2.2 pfbga-180 pin package marking
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-45 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5.3 thermal resistance of the package the chip temperature of lsi devices tends to increase with the power consumed on the chip. the chip temperature when encapsulated in a package is calculated from its ambient temperature (ta), the thermal resistance of the package ( ), and power dissipation (p d ). chip temperature (tj) = ta + (p d ) [ c] when used under normal operating conditions, make sure that the chip temperature (tj) is 100 c or less. thermal resistance of the qfp24-144 pin package 1. when mounted on a board (windless condition) thermal resistance ( j-a) = 33.3 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114 76 1.6 mm thick, fr4/4 layered board). 2. when suspended alone (windless condition) thermal resistance = 90C100 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. thermal resistance of the pfbga-180 pin package 1. when mounted on a board (windless condition) thermal resistance ( j-a) = 30 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114.5 101.5 1.6 mm thick, fr4/4 layered board). 2. when suspended alone (windless condition) thermal resistance = 165 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. note : the thermal resistance of the package varies significantly depending on how it is mounted on the board and whether forcibly air-cooled.
i s1c33e08 specifications: pin description i-3-46 epson s1c33e08 technical manual i.3.6 pad layout x y (0, 0) 4.70 mm 4.70 mm 1 5 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 125 45 50 55 60 65 70 75 80 130 135 140 145 150 155 160 165 168 pad opening (x y) 104 m 104 m: pad no. 1, 42, 43, 84, 85, 126, 127, 168 80 m 104 m: pad no. 2C41, 86C125 104 m 80 m: pad no. 44C83, 128C167 figure i.3.6.1 pad layout diagram
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-47 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i. 3.6.1 pad coordinate (unit: mm) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p ad name #ce9 (p55/card0) a18 (p46/tft_ctl2) a19 (p45/fpd a t11) a20 (p44/fpd a t10) a21 (p43/fpd a t9) a22 (p42/fpd a t8) v ss p30 (card2/#dmareq0) p31 (card3/#dmareq1) p32 (card4/#dmareq2) p33 (card5/#dmareq3) p00 (sin0/#dmaa ck2) p01 (sout0/#dmaa ck3) p02 (#sclk0/#dmaend2) p03 (#srd y0/#dmaend3) v ddh p04 (sin1/i2s_sdo) p05 (sout1/i2s_ws) p06 (#sclk1/i2s_sck) p07 (#srd y1/i2s_mclk) p10 (tm0/sin0/#dmaend0) p11 (tm1/sout0/#dmaend1) v dd p12 (tm2/#sclk0/#dmaa ck0) p13 (tm3/#srd y0/#dmaa ck1) p14 (tm4/sin1) dst0 (p15/tm5/sout1/tft_ctl0) dst1 (p16/dcsio0/#sclk1/tft_ctl3) dpco (p17/dcsio1/#srd y1/tft_ctl2) v ddh v ddh dsio (p34) dst2 (p36) dclk (p35) pb0 (fpd a t8/i2s_sdo/card2) p64 (#w ait) pb1 (fpd a t9/i2s_ws/card3) v ss p65 (sdi/fpd a t8) pb2 (fpd a t10/i2s_sck/card4) p66 (sdo/fpd a t9) pb3 (fpd a t11/i2s_mclk/card5) p67 (spi_clk/fpd a t10) v dd rtc_clki rtc_clko v ss plv ss vcp plv dd p ad name test0 boot1 av dd p74 (ain4/excl5) p73 (ain3) p72 (ain2) p71 (ain1) p70 (ain0) p80 (fpframe) p81 (fpline) p82 (fpshift) p83 (fpdrd y/tft_ctl1/bclk) p84 (dcsio0/fpd a t11) p85 (dcsio1) v dd mclki mclko v ss burnin p90 (fpd a t0) p91 (fpd a t1) p92 (fpd a t2) p93 (fpd a t3) v ddh pa0 (tft_ctl0) p94 (fpd a t4) pa1 (fpd a t8/tft_ctl0) p95 (fpd a t5) pa2 (fpd a t9/tft_ctl1) p96 (fpd a t6) pa3 (fpd a t10/tft_ctl2/card0) p97 (fpd a t7) pa4 (fpd a t11/tft_ctl3/card1) #reset #nmi v dd usbdm usbdp n.c. usbvbus n.c. v ddh p60 (sin2/dcsio0/excl0) p61 (sout2/dcsio1/excl1) p62 (#sclk2/#adtrg/cmu_clk) p63 (#srd y2/wdt_clk/#wdt_nmi) boot0 v ss d0 d1 x -2.02 -1.80 -1.68 -1.58 -1.49 -1.40 -1.31 -1.22 -1.13 -1.04 -0.95 -0.86 -0.77 -0.68 -0.59 -0.50 -0.41 -0.32 -0.23 -0.14 -0.05 0.05 0.14 0.23 0.32 0.41 0.50 0.59 0.68 0.77 0.86 0.95 1.04 1.13 1.22 1.31 1.40 1.49 1.58 1.68 1.80 2.02 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 y -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.02 -1.80 -1.68 -1.58 -1.49 -1.40 -1.31 -1.22 x 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.02 1.80 1.68 1.58 1.49 1.40 1.31 1.22 1.13 1.04 0.95 0.86 0.77 0.68 0.59 0.50 y -1.13 -1.04 -0.95 -0.86 -0.77 -0.68 -0.59 -0.50 -0.41 -0.32 -0.23 -0.14 -0.05 0.05 0.14 0.23 0.32 0.41 0.50 0.59 0.68 0.77 0.86 0.95 1.04 1.13 1.22 1.31 1.40 1.49 1.58 1.68 1.80 2.02 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23
i s1c33e08 specifications: pin description i-3-48 epson s1c33e08 technical manual no. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 no. 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 p ad name d2 d3 v dd d4 d5 d6 d7 v ddh d8 d9 d10 d11 v dd d12 d13 d14 d15 v ss p20 (sdcke) sdclk (p21) p22 (#sdcs) v ddh p23 (#sdras/tft_ctl1) p24 (#sdcas) p25 (#sd we) v ss p26 (dqml) p27 (dqmh) a14 a15 a16/dqml a17/dqmh #ce7 (p53/sd a10) a0/#bsl p ad name v ss v ss a1 a2 a3 a4 a5 v dd v dd a6 a7 a8 a9 v ddh v ddh a10 a11 (p47) a12 a13 a23 (p41/#sdras/excl3) a24 (p40/#sdcas/ excl4) v ss v ss #ce10 (p57) #rd #wrl #wrh/#bsh #ce11 (p56) p52 (bclk/#ce6/cmu_clk) v dd #ce4 (p50/card0) #ce5 (p51/card1) #ce8 (p54/card1) v ddh x 0.41 0.32 0.23 0.14 0.05 -0.05 -0.14 -0.23 -0.32 -0.41 -0.50 -0.59 -0.68 -0.77 -0.86 -0.95 -1.04 -1.13 -1.22 -1.31 -1.40 -1.49 -1.58 -1.68 -1.80 -2.02 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 y 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.02 1.80 1.68 1.58 1.49 1.40 1.31 1.22 x -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 y 1.13 1.04 0.95 0.86 0.77 0.68 0.59 0.50 0.41 0.32 0.23 0.14 0.05 -0.05 -0.14 -0.23 -0.32 -0.41 -0.50 -0.59 -0.68 -0.77 -0.86 -0.95 -1.04 -1.13 -1.22 -1.31 -1.40 -1.49 -1.58 -1.68 -1.80 -2.02
i s1c33e08 specifications: power supply s1c33e08 technical manual epson i-4-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.4 power supply this section explains the operating voltage of the s 1c33e08. i.4.1 power supply pins the s1c33e08 has the power supply pins shown in table i.4.1.1. table i.4.1.1 power supply pins function po wer supply (+) f or core (1.8 v) po wer supply (+) f or i/o (3.3 v) po wer supply (C); gnd po wer supply (+) f or pll (pl v dd = v dd ) po wer supply (C) f or pll (pl v ss = v ss ) po wer supply (+) f or analog system and ain0Cain4 (3.3 v, av dd = v ddh ) qfp 23,38,59,86,96,123 16,30,67,91,105,128 7,41,62,81,101,117,135 44 42 47 pin no. pin name v dd v ddh v ss pl v dd pl v ss av dd pfbga d7,e6,e7,f10,f11,g4, g11,h4,h5,k7,n2,n8 d8,e8,e9,f4,f5,g5,g10, h10,h11,k8,k9,l9 d4,d5,d6,d11,e5,e10, e11,j5,j10,j11,k5,k6, k10,k11,n3,n9 p5 p4 p6 i/o interface circuit cpu core internal logic circuits v dd 1.65 to 1.95 v (1.70 to 1.90 v ? 1 ) v ss gnd plv dd 1.65 to 1.95 v v ddh 2.70 to 3.60 v (3.00 to 3.60 v ? 2 ) plv ss gnd oscillator circuits pll ? 1 when the ceramic oscillator circuit is used ? 2 when the usb function controller is used analog circuits (a/d converter) av dd 2.70 to 3.60 v figure i.4.1.1 power supply system
i s1c33e08 specifications: power supply i-4-2 epson s1c33e08 technical manual i.4.2 operating voltage (v dd , v ss ) the core cpu and internal logic circuits operate with a voltage supplied between the v dd and v ss pins. the following operating voltage can be used: v dd = 1.65 v to 1.95 v (1.8 v 0.15 v, v ss = gnd) or v dd = 1.70 v to 1.90 v (1.8 v 0.10 v, v ss = gnd) when the ceramic oscillator circuit is used note : the s1c33e08 qfp package has six v dd pins and seven v ss pins; the pfbga package has 12 v dd pins and 16 v ss pins. be sure to supply the operating voltage to all the pins. do not open any of them. i.4.3 power supply for pll (plv dd , plv ss ) the pll power supply pins (plv dd , plv ss ) are provided separately from the v dd and v ss pins in order that the digital circuits do not affect the pll circuit. supply the same voltage level as the v dd to the plv dd pin. plv dd = v dd , plv ss = v ss noise on the pll power lines decrease the pll output precision, so use a stabilized power supply and make the board pattern with consideration given to that. i.4.4 power supply for i/o interface (v ddh ) the v ddh voltage is used for interfacing with external i/o signals. for the output interface of the s 1c33e08 , the v ddh voltage is used as high level and the v ss voltage as low level. the v ss pin is used for the ground common with v dd . the following voltage is enabled for v ddh : v ddh = 2.70 v to 3.60 v (v ss = gnd) when the usb function controller is not used or v ddh = 3.00 v to 3.60 v (3.3 v 0.3 v, v ss = gnd) when the usb function controller is used notes : ? the s1c33e08 qfp package has six v ddh pins; the pfbga package has 12 v ddh pins. be sure to supply the operating voltage to all the pins. do not open any of them. ? when an external clock is input to the mclki or rtc_clki pin, the clock signal level must be v dd . i.4.5 power supply for analog circuits (av dd ) the analog power supply pin (av dd ) is provided separately from the v dd and v ddh pins in order that the digital circuits do not affect the analog circuit (a/d converter). the av dd pin is used to supply an analog power voltage and the v ss pin is used as the analog ground. the following voltage is enabled for av dd : av dd = 2.70 v to 3.60 v (3.0/3.3 v 0.3 v, v ss = gnd) note : be sure to supply v ddh to the av dd pin when the analog circuit is not used. noise on the analog power lines decrease the a/d converting precision, so use a stabilized power supply and make the board pattern with consideration given to that.
i s1c33e08 specifications: power supply s1c33e08 technical manual epson i-4-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.4.6 precautions on power supply power-on sequence in order to operate the device normally, supply power in accordance with the following timing. v ddh , av dd v dd , plv dd osc3 #reset v dd min. t vdd t sta3 t rst figure i.4.6.1 power-on sequence (1) t vdd : elapsed time until the power supply stabilizes after power-on supply power in the following sequence (or simultaneously). power-on: v dd and plv dd (internal) v ddh and av dd (i/o) apply the input signal (2) t sta 3 : time at which osc 3 oscillation starts (3) t rst : minimum reset pulse width time at which the clock supplied to the chip stabilizes plus at least six clocks; keep the #reset signal low. power-off sequence shut off the power supply in the following sequence (or simultaneously). power-off: turn off the input signal av dd and v ddh (i/o) plv dd and v dd (internal) latch-up the cmos device may be in the latch-up condition. this is the phenomenon caused by conduction of the parasitic pnpn junction (thyristor) contained in the cmos ic, resulting in a large current between v dd and v ss and leading to breakage. latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows into the internal element, or when the voltage at the v dd pin exceeds the rated value and the internal element is in the breakdown condition. in the latter case, even if the application of a voltage exceeding the rated value is instantaneous, the current remains high between v dd and v ss once the device is in the latch-up condition. as this may result in heat generation or smoking, the following points must be taken into consideration: (1 ) the voltage level at the input / output must not exceed the range specified in the electrical characteristics. in other words, it must be below the power-supply voltage and above v ss . the power-on timing should also be taken into consideration. (2 ) abnormal noise must not be applied to the device. (3 ) the potential at the unused input should be fixed at v dd , v ddh , av dd , or v ss . (4) no outputs should be shorted.
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i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5 cpu core and bus architecture the s1c33e08 contains the c33 pe core as its core processor. the c 33 pe (processor element) core is a seiko epson original 32 -bit risc-type core processor for the s1c33 family microprocessors. based on the c 33 std core cpu features, some useful c33 adv core functions/ instructions were added and some of the infrequently used ones in general applications are removed to realize a high cost-performance core unit with high processing speed. the c 33 pe core has been designed with optimization for embedded applications (full rtl design) in mind to short development time and to reduce cost. as the principal instructions are object-code compatible with the c 33 std core cpu, the software assets that the user has accumulated in the past can be effectively utilized. for details of the c 33 pe core, refer to the s1c33 family c33 pe core manual. i.5.1 features of the c33 pe core processor type ? seiko epson original 32-bit risc processor ? 32-bit internal data processing ? contains a 32-bit 8-bit multiplier operating-clock frequency ? dc to 66 mhz or higher (depending on the processor model and process technology) instruction set ? code length 16 -bit fixed length ? number of instructions 125 ? execution cycle main instructions executed in one cycles ? extended immediate instructions immediate extended up to 32 bits ? multiplication instructions multiplications for 16 16 and 32 32 bits supported register set ? 32 -bit general-purpose registers ? 32 -bit special registers memory space and external bus ? instruction, data, and i/o coexisting linear space ? up to 4g bytes of memory space ? harvard architecture using separated instruction bus and data bus interrupts ? reset, nmi, and 240 external interrupts supported ? four software exceptions ? three instruction execution exceptions ? direct branching from vector table to interrupt handler routine power-down mode ? halt mode ? sleep mode
i s1c33e08 specifications: cpu core and bus architecture i-5-2 epson s1c33e08 technical manual i.5.2 cpu registers the c33 pe core contains 16 general-purpose registers and 8 special registers. r15 r14 r13 r12 r11 r10 r4 r5 r6 r7 r8 r9 r3 r2 r1 r0 bit 31 bit 0 general-purpose registers pc ttbr bit 31 #15 #11 #10 #8 #3 #2 #1 #0 #15 #14 #13 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 bit 0 ahr alr psr sp idir dbbr special registers figure i.5.2.1 registers
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.3 instruction set the c 33 pe core instruction set consists of the function-extended instruction set of the c33 std core cpu and the new instructions, in addition to the conventional s 1c33 -series instructions. some instructions of the c33 std core cpu are deleted. as the c 33 pe core is object-code compatible with the c33 std core cpu, software assets can be transported from the s1c33 series to the c33 pe model easily, with minimal modifications required. all of the instruction codes are fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle. for details, refer to the s1c33 family c33 pe core manual. table i.5.3.1 s1c33-series-compatible instructions classification ar ithmetic operation branch function addition between general-pur pose registers addition of a general-pur pose register and immediate addition of sp and immediate (with immediate z ero-e xtended) addition with carr y between general-pur pose registers subtraction between general-purpose registers subtraction of general-pur pose register and immediate subtraction of sp and immediate (with immediate z ero-e xtended) subtraction with carr y between general-pur pose registers ar ithmetic compar ison between general-pur pose registers ar ithmetic compar ison of general-pur pose register and immediate (with immediate z ero-e xtended) signed integer multiplication (16 bits 16 bits 32 bits) unsigned integer multiplication (16 bits 16 bits 32 bits) signed integer multiplication (32 bits 32 bits 64 bits) unsigned integer multiplication (32 bits 32 bits 64 bits) pc relativ e conditional jump branch condition: !z & !(n ^ v) dela y ed branching possib le pc relativ e conditional jump branch condition: !(n ^ v) dela y ed branching possib le pc relativ e conditional jump branch condition: n ^ v dela y ed branching possib le pc relativ e conditional jump branch condition: z | n ^ v dela y ed branching possib le pc relativ e conditional jump branch condition: !z & !c dela y ed branching possib le pc relativ e conditional jump branch condition: !c dela y ed branching possib le pc relativ e conditional jump branch condition: c dela y ed branching possib le pc relativ e conditional jump branch condition: z | c dela y ed branching possib le pc relativ e conditional jump branch condition: z dela y ed branching possib le pc relativ e conditional jump branch condition: !z dela y ed branching possib le pc relativ e jump dela y ed branching possib le absolute jump dela y ed branching possib le pc relativ e subroutine call dela y ed call possib le absolute subroutine call dela y ed call possib le subroutine retur n dela y ed retur n possib le retur n from interr upt or e xception handling retur n from the deb ug processing routine softw are e xception deb ug e xception add adc sub sbc cmp mlt.h mltu.h mlt.w mltu.w jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d jp jp.d call call.d ret ret.d reti retd int brk %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,sign6 %rd,%rs %rd,%rs %rd,%rs %rd,%rs sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 %rb sign8 %rb imm2 mnemonic
i s1c33e08 specifications: cpu core and bus architecture i-5-4 epson s1c33e08 technical manual classification data transf er system control immediate e xtension bit manipulation other function general-pur pose register (b yte) general-pur pose register (sign-e xtended) memor y (b yte) general-pur pose register (sign-e xtended) p ostincrement possib le stac k (b yte) general-pur pose register (sign-e xtended) general-pur pose register (b yte) memor y p ostincrement possib le general-pur pose register (b yte) stac k general-pur pose register (b yte) general-pur pose register (z ero-e xtended) memor y (b yte) general-pur pose register (z ero-e xtended) p ostincrement possib le stac k (b yte) general-pur pose register (z ero-e xtended) general-pur pose register (halfword) general-pur pose register (sign-e xtended) memor y (halfword) general-pur pose register (sign-e xtended) p ostincrement possib le stac k (halfword) general-pur pose register (sign-e xtended) general-pur pose register (halfword) memor y p ostincrement possib le general-pur pose register (halfword) stac k general-pur pose register (halfword) general-pur pose register (z ero-e xtended) memor y (halfword) general-pur pose register (z ero-e xtended) p ostincrement possib le stac k (halfword) general-pur pose register (z ero-e xtended) general-pur pose register (word) general-pur pose register immediate general-pur pose register (sign-e xtended) memor y (word) general-pur pose register p ostincrement possib le stac k (word) general-pur pose register general-pur pose register (word) memor y p ostincrement possib le general-pur pose register (word) stac k no operation hal t sleep extend operand in the f ollo wing instr uction t est a specified bit in memor y data clear a specified bit in memor y data set a specified bit in memor y data in ve rt a specified bit in memor y data byte wise sw ap on b yte boundar y in word push general-pur pose registers %rs C%r0 onto the stac k p op data f or general-pur pose registers %rd C%r0 off the stac k ld.b ld.ub ld.h ld.uh ld.w nop halt slp ext btst bclr bset bnot swap pushn popn %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb ]+,%rs [%sp+imm6 ],%rs %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb]+,%rs [%sp+imm6 ],%rs %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] %rd,%rs %rd,sign6 %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb]+,%rs [%sp+imm6 ],%rs imm13 [%rb ],imm3 [%rb ],imm3 [%rb ],imm3 [%rb ],imm3 %rd,%rs %rs %rd mnemonic the symbols in the above table each have the meanings specified below. table i.5.3.2 symbol meanings symbol %rs %rd %ss %sd [ %rb ] [ %rb ]+ %sp imm2,imm4,imm3, imm5,imm6,imm10, imm13 sign6,sign8 description general-pur pose register , source general-pur pose register , destination special register , source special register , destination general-pur pose register , indirect addressing general-pur pose register , indirect addressing with postincrement stac k pointer unsigned immediate (numerals indicating bit length) ho we ve r, numerals in shift instr uctions indicate the number of bits shifted, while those in bit manipulation indicate bit positions . signed immediate (numerals indicating bit length)
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i.5.3.3 function extended instructions classification logical operation shift and rotate data transf er function logical and between general-pur pose registers logical and of general-pur pose register and immediate logical or between general-pur pose registers logical or of general-pur pose register and immediate exclusiv e or between general-pur pose registers exclusiv e or of general-pur pose register and immediate logical in v ersion between general-pur pose registers (1's complement) logical in v ersion of general-pur pose register and immediate (1's complement) logical shift to the r ight (bits 0C31 shifted as specified by the register) logical shift to the r ight (bits 0C31 shifted as specified by immediate) logical shift to the left (bits 0C31 shifted as specified by the register) logical shift to the left (bits 0C31 shifted as specified by immediate) ar ithmetic shift to the r ight (bits 0C31 shifted as specified by the register) ar ithmetic shift to the r ight (bits 0C31 shifted as specified by immediate) ar ithmetic shift to the left (bits 0C31 shifted as specified by the register) ar ithmetic shift to the left (bits 0C31 shifted as specified by immediate) rotate to the r ight (bits 0C31 rotated as specified by the register) rotate to the r ight (bits 0C31 rotated as specified by immediate) rotate to the left (bits 0C31 rotated as specified by the register) rotate to the left (bits 0C31 rotated as specified by immediate) special register (word) general-pur pose register general-pur pose register (word) special register extended function the v flag is cleared after the instr uction has been ex ecuted. f or rotate/shift operation, it has been made possib le to shift 9C31 bits . the number of special registers that can be used to load data has been increased. and or xor not srl sll sra sla rr rl ld.w %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%ss %sd,%rs mnemonic
i s1c33e08 specifications: cpu core and bus architecture i-5-6 epson s1c33e08 technical manual table i.5.3.4 instructions added to the c33 pe core classification branch system control coprocessor control other function pc relativ e jump dela y ed branching possib le set a specified bit in psr clear a specified bit in psr load data from coprocessor store data in coprocessor ex ecute coprocessor load c, v, z, and n flags from coprocessor byte wise sw ap on halfword boundar y in word push single general-pur pose register p op single general-pur pose register push special registers %ssCalr onto the stac k p op data f or special registers %sdCalr off the stac k jpr jpr.d psrset psrclr ld.c ld.c do.c ld.cf swaph push pop pushs pops %rb imm5 imm5 %rd,imm4 imm4,%rs imm6 %rd,%rs %rs %rd %ss %sd mnemonic table i.5.3.5 instructions removed classification ar ithmetic operation other function first step in signed integer division first step in unsigned integer division ex ecution of step division data correction f or the result of signed integer division 1 data correction f or the result of signed integer division 2 bitwise sw ap ev er y b yte in word multiply-accumulate operation 16 bits 16 bits + 64 bits 64 bits search f or bits whose v alue = 0 search f or bits whose v alue = 1 div0s div0u div1 div2s div3s mirror mac scan0 scan1 %rs %rs %rs %rs %rd,%rs %rs %rd,%rs %rd,%rs mnemonic
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.4 trap table the c33 pe core allows the base (starting) address of the trap table to be set by the ttbr register. after an initial reset, the ttbr register is set to 0xc00000. therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the above address. bits 9 to 0 in the ttbr register are fixed at 0 . therefore, the trap table starting address always begins with a 1kb boundary address. table i.5.4.1 trap table idma ch. C C C C C C C C C C C C C C 1 2 3 4 C C 5 6 C C C C 7 8 C 9 10 C 11 12 C 13 14 C 15 16 C 17 18 C priority 1 C 4 3 C 2 5 6 C high lo w v ector number (he x address) 0(base) 1 2(base+8) 3(base+0c) 4C5 6(base+18) 0x60000 7(base+1c) 8C10 11(base+2c) 12(base+30) 13(base+34) 14(base+38) 15(base+3c) 16(base+40) 17(base+44) 18(base+48) 19(base+4c) 20(base+50) 21(base+54) 22(base+58) 23(base+5c) 24(base+60) 25(base+64) 26(base+68) 27C29 30(base+78) 31(base+7c) 32C33 34(base+88) 35(base+8c) 36C37 38(base+98) 39(base+9c) 40C41 42(base+a8) 43(base+a c) 44C45 46(base+b8) 47(base+bc) 48C49 50(base+c8) 51(base+cc) 52C55 exception/interrupt name (peripheral cir cuit) reset reser ve d ext e xception undefined instr uction e xception reser ve d address misaligned e xception deb ugging e xception nmi reser ve d illegal interr upt e xception softw are e xception 0 softw are e xception 1 softw are e xception 2 softw are e xception 3 po rt input interr upt 0 po rt input interr upt 1 po rt input interr upt 2 po rt input interr upt 3 ke y input interr upt 0 ke y input interr upt 1 high-speed dma ch.0 high-speed dma ch.1 high-speed dma ch.2 high-speed dma ch.3 intelligent dma reser ve d 16-bit timer 0 reser ve d 16-bit timer 1 reser ve d 16-bit timer 2 reser ve d 16-bit timer 3 reser ve d 16-bit timer 4 reser ve d 16-bit timer 5 reser ve d cause of e xception/interrupt lo w input to the reset pin C ext instr uction (illegal use) undefined instr uction C memor y access instr uction brk instr uction, etc. lo w input to the #nmi pin or w atchdog timer ov erflo w C occurrence of illegal interr upt from itc int instr uction int instr uction int instr uction int instr uction edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) rising or f alling edge rising or f alling edge high-speed dma ch.0, end of transf er high-speed dma ch.1, end of transf er high-speed dma ch.2, end of transf er high-speed dma ch.3, end of transf er intelligent dma, end of transf er C timer 0 compare-match b timer 0 compare-match a C timer 1 compare-match b timer 1 compare-match a C timer 2 compare-match b timer 2 compare-match a C timer 3 compare-match b timer 3 compare-match a C timer 4 compare-match b timer 4 compare-match a C timer 5 compare-match b timer 5 compare-match a C
i s1c33e08 specifications: cpu core and bus architecture i-5-8 epson s1c33e08 technical manual idma ch. C 23 24 C C 25 26 C 27 C C 28 29 30 31 C 33 C C 34 35 C 36 37 C 38 39 40 41 42 43 44 45 C 46 C priority high lo w v ector number (he x address) 56(base+e0) 57(base+e4) 58(base+e8) 59 60(base+f0) 61(base+f4) 62(base+f8) 63(base+fc) 64(base+100) 65(base+104) 66C67 68(base+110) 69(base+114) 70(base+118) 71(base+11c) 72(base+120) 73(base+124) 74C75 76(base+130) 77(base+134) 78(base+138) 79C80 81(base+144) 82(base+148) 83 84(base+150) 85(base+154) 86(base+158) 87(base+15c) 88(base+160) 89(base+164) 90(base+168) 91(base+16c) 92C93 94(base+178) 95C107 exception/interrupt name (peripheral cir cuit) ser ial interf ace ch.0 reser ve d ser ial interf ace ch.1 a/d con ve r ter rt c reser ve d po rt input interr upt 4 po rt input interr upt 5 po rt input interr upt 6 po rt input interr upt 7 reser ve d lcdc reser ve d ser ial interf ace ch.2 reser ve d spi reser ve d po rt input interr upt 8 spi po rt input interr upt 9 usb pdreq po rt input interr upt 10 usb po rt input interr upt 11 dcsio po rt input interr upt 12 po rt input interr upt 13 po rt input interr upt 14 po rt input interr upt 15 reser ve d i 2 s interf ace reser ve d cause of e xception/interrupt receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e error receiv e b uff er full tr ansmit b uff er empty result out of range (upper-limit and lo wer-limit) end of con v ersion 1/64 second, 1 second, 1 minuet, or 1 hour count up C edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C end of frame C receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e dma request tr ansmit dma request C edge (r ising or f alling) or le v el (high or lo w) spi interr upt (d[1:0]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb dma request (d[3:2]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb interr upt (d[5:4]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) dcsio interr upt (d[7:6]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C i 2 s fifo empty C notes : ? the mp3 decoder bios (mp3 decoder module) uses the hsdma ch.0 , ch.1 and i 2 s and their interrupts for output data requests. therefore, these dma channels and interrupts cannot be used in the user program. ? idma ch.19C22, 32, 47C53 are reserved.
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.5 power-down mode the c33 pe core supports two power-down modes: halt and sleep modes. halt mode program execution is halted at the same time that the c 33 pe core executes the halt instruction, and the processor enters halt mode. halt mode commonly turns off only the c 33 pe core operation. see section iii.1.11, standby modes, for details. sleep mode program execution is halted at the same time the c 33 pe core executes the slp instruction, and the processor enters sleep mode. sleep mode commonly turns off the c 33 pe core and on-chip peripheral circuit operations, thereby it significantly reduces the current consumption in comparison to the halt mode. see section iii. 1.11, standby modes, for details. canceling halt or sleep mode initial reset, maskable external interrupts, nmi, and debug exceptions are commonly used for canceling halt and sleep modes. the interrupt enable/disable status set in the processor does not affect the cancellation of halt or sleep mode even if an interrupt signal is used as the cancellation. in other words, interrupt signals are able to cancel halt and sleep modes even if the ie flag in psr or the interrupt enable bits in the interrupt controller (depending on the implementation) are set to disable interrupts. when the processor is taken out of halt or sleep mode using an interrupt that has been enabled (by the interrupt controller and ie flag), the corresponding interrupt handler routine is executed. therefore, when the interrupt handler routine is terminated by the reti instruction, the processor returns to the instruction next to halt or slp . when the interrupt has been disabled, the processor restarts the program from the instruction next to halt or slp after the processor is taken out of halt or sleep mode.
i s1c33e08 specifications: cpu core and bus architecture i-5-10 epson s1c33e08 technical manual i.5.6 debug mode the c33 pe core has debug mode to assist in software development by the user. the debug mode provides the following functions: ? instruction break a debug exception is generated before the set instruction address is executed. an instruction break can be set at three addresses. ? data break a debug exception is generated when the set address is accessed for read or write. a data break can be set at only one address. ? single step a debug exception is generated every instruction executed. ? forcible break a debug exception is generated by an external input signal. ? bus break a debug exception is generated when the data of the selected bus matches the set value. ? bus trace the value of the selected bus is traced. ? pc trace the status of instruction execution by the processor is traced. when a debug exception occurs, the processor performs the following processing: (1 ) suspends the instruction currently being executed. a debug exception is generated at the end of the e stage of the currently executed instruction, and is accepted at the next rise of the system clock. (2 ) saves the contents of the pc and r0 , in that order, to the addresses specified below. pc 0x00060008 r 0 0x0006000c (3 ) loads the debug exception vector located at the address 0 x 00060000 to pc and branches to the debug exception handler routine. in the exception handler routine, the retd instruction should be executed at the end of processing to return to the suspended instruction. when returning from the exception by the retd instruction, the processor restores the saved data in order of the r0 and the pc. neither hardware interrupts nor nmi interrupts are accepted during a debug exception.
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.7 bus architecture pe_e08_cpu lcdc area 6 ivram (12kb) ivram arbiter dqb dqb arbiter iqb dst ram (2kb) area 3 sdramc_ip mux exter nal memor y i/f a6dec sd app1 < < < x32 < < cpu_ahb lcdc_ahb lcdc_amb a: master dma gp: master 2 internal peripheral modules external de vices external bu s sapb bu s s1c33pe_amb a: master 1 sd app2 sdramc sramc (sapb bridge) hsdma idma dma gp registers dma gp x32 x32 x32 x32 x32 x16 x16 x16 x32 figure i.5.7.1 s1c33e08 bus architecture i.5.7.1 32-bit high-speed bus since the ivram (internal video ram) or an external sdram may be simultaneously accessed from the cpu and the lcdc, the s 1c33e08 adopts a dual 32 -bit high-speed bus system that consists of the cpu_ahb bus and lcdc_ahb bus to reduce bus occupancy by one bus master. the c 33 pe core, dmac, sramc, instruction/data caches in sdramc, ivram arbiter and dst ram in area 3 are connected to the cpu_ahb bus. usually the c33 pe core is the bus master of the cpu_ahb bus and the ownership of the bus is delegated to the dmac when a dma request is generated. the lcdc, ivram arbiter and lcdc data cache in sdramc are connected to the lcdc_ahb bus. the lcdc_ahb bus master is always the lcdc. the ivram arbiter is connected to both the cpu_ahb and lcdc_ahb buses and it arbitrates accesses to the ivram from the cpu and lcdc. the lcdc has higher priority than the cpu for the ivram access authorization as it must refresh the lcd display. for details of the ivram arbiter, see section viii. 2, ivram and ivram arbiter. likewise the sdramc is connected to the both buses allowing the cpu and lcdc to access the external sdram. also in this case the lcdc has higher priority. the bus arbiter in the sdramc arbitrates the ownership of the bus between the cpu and lcdc. for details of the bus arbiter, see section ii. 4.3, bus arbiter.
i s1c33e08 specifications: cpu core and bus architecture i-5-12 epson s1c33e08 technical manual i.5.7.2 sapb bus the sapb bus is used to access the internal peripheral modules located in area 6 . the sramc functions as a bridge between the cpu_ahb bus and sapb bus. i.5.7.3 external bus the s1c33e08 external bus is configured with a 25 -bit address bus and a 16 -bit data bus. the external sdram is accessed via the sdramc and other devices are accessed via the sramc. the bus arbiter in the sdramc arbitrates the access authorization for t he external bus. for more information on the external memory, see section i. 6, memory map, section ii.3, sram controller (sramc), and section ii.4, sdram controller (sdramc).
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.8 chip id the s 1c33e08 has chip id bits shown below that allow the application software to identify cpu type, model, and chip version. core id bits (d[7:0]/0x20000) these bits provide an 8-bit id code that indicates the chip core type. id chip core type 0x02 c33 standard macro core (c33 std core) 0x03 c33 mini-macro core 0x04 c33 advanced macro core (c33 adv core) 0x05 c33 pe core 0x06 c33 pe little endian core the s 1c33e08 has adopted the c33 pe little endian core, so the chip core id is 0x06. product series id bits (d[ 7:0]/0x20001) these bits provide an 8-bit id code that indicates the product series of the s1c33 family. id product series 0x03 s1c333xx series 0x04 s1c334xx series 0x0 e s1c33exx series 0x15 s1c33lxx series the product series id of the s 1c33e08 is 0x0e. model id bits (d[7:0]/0x20002) these bits provide an 8-bit id code that indicates the model. the model id of the s 1c33e07/e08 is 0x07. version bits (d[ 7:0]/0x20003) these bits provide an 8 -bit id code that indicates the version number. 0x22 is a version number.
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i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6 memory map figure i. 6.1 shows a memory map of the entire address space of the s1c33e08 . figure i.6.2 shows a memory map of internal memory and the internal i/o space of the s1c33e08. area 13 0x02ff ffff 0x0200 0000 area 12 0x01ff ffff 0x0180 0000 area 11 0x017f ffff 0x0100 0000 area 10 0x00ff ffff 0x00c0 0000 area 9 0x00bf ffff 0x0080 0000 area 8 0x007f ffff 0x0060 0000 area 7 0x005f ffff 0x0040 0000 area 6 0x003f ffff 0x0030 0000 ip and peripherals (reserved for ip and peripherals) area 5 0x002f ffff 0x0020 0000 area 4 0x001f ffff 0x0010 0000 area 3 0x000f ffff 0x0008 0000 internal ram area area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 1 0x0005 ffff 0x0002 0000 specific rom area (reserved) area 0 0x0001 ffff 0x0000 0000 area 22 0xffff ffff 0x8000 0000 area 21 0x7fff ffff 0x4000 0000 area 20 0x3fff ffff 0x2000 0000 area 19 0x1fff ffff 0x1000 0000 area 18 0x0fff ffff 0x0c00 0000 area 17 0x0bff ffff 0x0800 0000 area 16 0x07ff ffff 0x0600 0000 area 15 0x05ff ffff 0x0400 0000 area 14 0x03ff ffff 0x0300 0000 internal ram area external memory 16m bytes external memory 8m bytes external memory 8m bytes external memory 4m bytes external memory 4m bytes external memory 2m bytes external memory 2m bytes external memory 1m bytes external memory 1m bytes external memory 2g bytes external memory 1g bytes external memory 512m bytes external memory 256m bytes external memory 64m bytes external memory 64m bytes external memory 32m bytes external memory 32m bytes external memory 16m bytes #ce10 #ce11 #ce11 #ce10 #ce9 #ce8 #ce7 #ce5 #ce4 #ce9 #ce7 * #ce8 #ce10 #ce7 #ce6 #ce6 #ce5 #ce5 #ce4 (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) 4-word gate rom (reserved) (reserved) (reserved) (reserved) (reserved) internal areas external areas usable as memory space for smartmedia (nand flash), compactflash, or pc card. ? see note below. figure i.6.1 general memory map notes : area 22 is assigned to #ce9 in default settings. note that area 22 will be reassigned to #ce7 when the sdramc is enabled. a minimum 20 k bytes of external ram is required for using the mp3 decoder bios.
i s1c33e08 specifications: memory map i-6-2 epson s1c33e08 technical manual area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 0 0x0001 ffff 0x0000 8000 0x0000 4fff 0x0000 2000 0x0000 1fff 0x0000 0000 a0ram (12kb) a0ram (8kb) (reserved) area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 ivram (12kb) dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) specific rom (reserved for firmware) (reserved) internal i/o 0x301c00C0x301c20 0x301b00C0x301b24 0x301a00C0x301aac 0x301900C0x301928 0x301800C0x30181c 0x301700C0x30171c 0x301600C0x301610 0x301500C0x301510 0x301120C0x30119e 0x301100C0x301105 0x300c40C0x300c4d 0x300c00C0x300c25 0x300b00C0x300b4f 0x300a00C0x300aff 0x300900C0x30099f 0x300780C0x3007ea 0x300660C0x30066c 0x300520C0x30055e 0x300380C0x3003d5 0x300300C0x30031b 0x300260C0x3002af 0x300010C0x300020 i 2 s interface clock management unit lcd controller real time clock dcsio spi sdram controller sram controller high-speed dma intelligent dma misc register (2) extended ports serial interface usb dma area usb function controller 16-bit timer watchdog timer a/d converter i/o ports card interface interrupt controller misc register (1) internal areas the 12kb ivram can be moved to area 0 for use as a general-purpose ram (a part of the a0ram) if the lcdc is not using the ivram. an lcdc register is used to configure ivram. figure i.6.2 internal area map (when mp3 decoder bios is not used) area 2 0x0007 ffff 0x0006 0000 area 0 0x0001 ffff 0x0000 0400 0x0000 03ff 0x0000 0000 a0ram (1kb) reserved for mp3 decoder area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 ivram (12kb) dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) specific rom (reserved for firmware) (reserved) reserved for debugging internal areas the mp3 decoder bios (mp3 decoder module) uses 7kb of a0ram (0x0400C0x1fff) and 12kb of ivram (located in area 0) as an mp3 work area. when using the mp3 calculation module only (when user's mp3 decoder routine is used), a0ram and ivram may be used in the user program. see figure i.6.2 figure i.6.3 internal area map (when mp3 decoder bios is used) the following describes the area configuration of the s 1c33e08.
i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6.1 boot address and gate rom when the chip is powered on or reset, the boot address is set to 0xc00000 (initial value of ttbr) by the c33 pe core. in the s 1c33e08 , a 4 -word gate rom is located at address 0xc00000 in area 10 (internal area), and the vectors written to it are used to start a boot sequence regardless whether an external memory is connected to area 10 or not. the vector written in the gate rom, which boots up the system, is determined by the input status of the boot pins. also the #ce 10 pin is used to set the boot mode. by setting these pins, the s1c33e08 boots up from a nand flash, spi-eeprom, pc (rs- 232 c), or an external nor-flash/rom. the boot sequence has been programmed in the specific rom located in area 1. tables i. 6.1.1 and i.6.1.2 list the pin configurations and the boot mode selected. for more information on boot, see appendix d, boot. table i.6.1.1 boot mode configuration (pfbga-180pin or die model) boo t1 pin 1 1 0 0 boot mode spi-eepr om pc rs232c nor flash/e xter nal ro m reser ve d large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash (< 1024 + 32 b ytes/page) boo t0 pin 1 0 1 0 #ce10 1 (input) 0 (input) output C 1 (input) 0 (input) boot code star t address 0x20010 in the inter nal r om (area 1) 0x2000c in the inter nal r om (area 1) C 0x20004 in the inter nal r om (area 1) mbr ex ecution address 0x0 in a0ram depending on the contents in 0xc00000 C 0x0 in a0ram table i.6.1.2 boot mode configuration (qfp-144pin model) boo t1 pin 1 0 boot mode nor flash/e xter nal ro m large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash (< 1024 + 32 b ytes/page) #ce10 output 1 (input) 0 (input) boot code star t address 0x2000c in the inter nal r om (area 1) 0x20004 in the inter nal r om (area 1) mbr ex ecution address depending on the contents in 0xc00000 0x0 in a0ram ? the qfp- 144 pin does not have the boot0 pin due to the limited number of pins available (boot 0 has been pulled down to v ss inside the ic). i.6.2 area 0 (a0ram) area 0 contains an 8k-byte high-speed ram (a0ram). its location address ranges from 0x0 to 0x1 fff. moreover, the s 1c33e08 has a built-in 12 k-byte ram (ivram) to be used as a video ram for the lcdc, which is located in area 3 by default. if ivram is not required for use as a video ram (e.g. when the lcdc is not used or when an external sdram is used as a video ram), ivram can be moved to area 0 to expand a0 ram into 20 k bytes. the lcdc provides the control bit iram (d 0 / 0 x 301 a 64 ) for this switch over. when iram = 0 (default), ivram is located in area 3 and when iram = 1 , ivram is located at 0x2000 to 0x4 fff in area 0 (immediately following 8 k-byte a0ram). ? iram : iram assign bit in the iram select register (d0/0x301a64) since a 0 ram (including ivram located in area 0 ) is accessed directly from the cpu without passing through the ahb bus, no wait cycles are inserted. a 0 ram is accessed in one cycle (with no wait cycle), regardless of whether accessed in units of bytes, half-words, or words. moreover, due to a harvard architecture, a 0 ram can be accessed simultaneously with the fetching of instructions from external memory (cache).
i s1c33e08 specifications: memory map i-6-4 epson s1c33e08 technical manual notes : ? a0 ram cannot contain idma control words or be specified as the source or destination of dma transfer. ? when the debug monitor s5u1c330m2d1 (mon33 ) is used to debug, addresses 0x0 to 0 xf are configured as an area for debugging. the s5u1c330m2d1 does not allow the user program to access this address range. when only the s 5u1c33001 h (icd33 ) is used for debugging, this area can be accessed by the user. ? the mp3 decoder bios (mp3 decoder module) uses 7 kb of a0 ram (0x0400C0x1 fff) and 12 kb of ivram (located in area 0 ) as an mp3 work area. when using the mp3 calculation module only (when user's mp 3 decoder routine is used), a0 ram and ivram may be used in the user program. i.6.3 area 1 (specific rom for firmware) area 1 contains a 64 k-byte mask rom. this rom is reserved for firmware to support booting and the mp3 decoder bios, therefore it does not contain a user program. the mp 3 decoder bios provides the mp3 data decoding and playback api functions. for details of the mp3 decoder, refer to section x. 1, mp3 decoder. i.6.4 area 2 (debug area) area 2 is a debugging-only area allocated for debugging resources. this area can only be accessed for writing in debug mode. make sure this area is not accessed from the user program or debugger. i.6.5 area 3 (ivram) 0x80000 to 0x82 fff in area 3 is allocated to the 12 k-byte ivram (internal video ram) by the default configuration. ivram can be used as a video ram for the lcdc. the lcdc and cpu access ivram through their respective 32 -bit ahb bus and the ivram arbiter that resolves bus conflicts between the lcdc and cpu. ivram located in area 3 can be accessed in a minimum of 2 -wait cycles. as described in section i. 6.2 , ivram can be located in area 0 for use as a high-speed general-purpose ram that allows no wait access when it is not used as a video ram. notes : ? a program cannot be executed in the ivram located in area 3. ? when using the mp3 decoder bios (mp3 decoder module), the ivram will be relocated to area 0 to be used as an mp3 work area by an api function. in this case, an external sdram must be used as the vram. i.6.6 area 3 (dst ram) 0x84000 to 0x847 ff in area 3 is allocated to the 2 k-byte dst ram (descriptor table ram). dst ram is provided for storing idma control words as a 0 ram cannot contain them. the memory space other than control words can be used as a general-purpose ram and may also be specified as the source and destination of dma transfer. dst ram can be accessed in a minimum of 2 -wait cycles. note : the upper 256 bytes (0x84700 to 0x847ff) in dst ram are reserved for use as the debugging area. the user program must be prohibited from accessing this area. however, specify 0x84780 for the debug ram address of the c33 das command in the debugger. c33 das 0x60000 0x84780 1
i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6.7 area 6 (i/o area) area 6 is allocated to the i/o area for s1c33e08 ip and peripheral circuits. although area 6 is one of the external memory areas, external memory cannot be accessed. for details of the internal peripheral circuits mapped to this area, see the description in chapters iii to ix. for details of a control register list, see i/o map in the appendix. i.6.8 external memory areas areas 4, 5 , and 7 to 22 can be used for external memory and other external devices. set up the sramc or sdramc according to specifications of the devices connected. although the internal address and internal data buses of the s 1c33e08 are both 32 bits wide, the maximum external data bus width is 16 bits (d[15:0 ]) and the maximum external address bus width is 25 bits (a[24:0 ]) due to the limited number of pins available. note : the mp3 decoder bios (mp3 decoder module) uses a minimum of 20kb area in the external ram. when using the mp3 calculation module only (when user's mp3 decoder routine is used), no external ram is required for the mp3 decoder bios.
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i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7 electrical characteristics i.7.1 absolute maximum rating item internal logic power voltage pll power voltage i/o power voltage analog power voltage input voltage analog input voltage high-level output current low-level output current storage temperature ( v ss =plv ss =0v ) symbol v dd plv dd v ddh av dd v i av in i oh i ol t stg rated value -0.3 to +2.5 -0.3 to +2.5 -0.3 to +4.0 -0.3 to +4.0 -0.3 to v dd h +0.5 -0.3 to av dd +0.3 -10 -40 10 40 -65 to +150 unit v v v v v v ma ma ma ma c condition 1 pin total of all pins 1 pin total of all pins ? i.7.2 recommended operating conditions item internal logic power voltage pll power voltage i/o power voltage analog power voltage input voltage analog input voltage cpu operating clock frequency bus operating clock frequency osc3 oscillation frequency osc3 external input clock frequency osc1 oscillation frequency operating temperature input rise time (normal input) input fall time (normal input) input rise time (schmitt input) input fall time (schmitt input) (v ss =plv ss =0v) symbol v dd plv dd v ddh av dd hv i lv i av in f cpu f bus f osc3 f eclk3 f osc1 ta t ri t fi t ri t fi max. 1.95 1.90 1.95 3.60 3.60 3.60 v ddh v dd av dd 60 60 48 48 C 85 70 50 50 5 5 unit v v v v v v v v v mhz mhz mhz mhz khz c c ns ns ms ms condition crystal or external clock ceramic oscillation when usb is not used when usb is used crystal or external clock ceramic oscillation typ. 1.80 1.80 1.80 C 3.30 C C C C C C C C 32.768 25 25 C C C C min. 1.65 1.70 1.65 2.70 3.00 2.70 v ss v ss v ss C C 5 2 C -40 0 C C C C ?
i s1c33e08 specifications: electrical characteristics i-7-2 epson s1c33e08 technical manual i.7.3 dc characteristics item input leakage current off-state leakage current high-level output voltage low-level output voltage high-level input voltage low-level input voltage positive trigger input voltage negative trigger input voltage hysteresis voltage pull-up resistor pull-down resistor high-level latching current low-level latching current high-level reversal current low-level reversal current input pin capacitance output pin capacitance i/o pin capacitance (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol i li i oz v oh v ol v ih v il v t+ v t- v h r pu r pd i bhh i bhl i bhho i bhlo c i c o c io max. 5 5 C 0.4 v ddh 0.8 2.7 1.8 C 288 144 346 144 -20 17 C C 8 8 8 unit a a v v v v v v v k ? k ? k ? k ? a a a a pf pf pf condition i oh =-1.7ma (2ma type), i oh =-3.5ma (4ma type), v dd =min. i ol =1.7ma (2ma type), i ol =3.5ma (4ma type), v dd =min. lvttl level, v ddh =max. lvttl level, v ddh =min. lvcmos schmitt lvcmos schmitt lvcmos schmitt v i =0v 100k ? type 50k ? type v i =v ddh 120k ? type 50k ? type pins with bus-hold latch, v i =1.9v, v ddh =min. pins with bus-hold latch, v i =0.8v, v ddh =min. pins with bus-hold latch, v i =0.8v, v ddh =max. pins with bus-hold latch, v i =1.9v, v ddh =max. f=1mhz, v ddh =0v f=1mhz, v ddh =0v f=1mhz, v ddh =0v typ. C C C C C C C C C 100 50 120 50 C C C C C C C min. -5 -5 v dd -0.4 C 2.0 v ss 1.2 0.5 0.2 50 25 60 25 C C -350 300 C C C ? note : see section i.3.4, input/output cells and input/output characteristics, for pin characteristics.
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.4 current consumption operating current item current consumption during cpu running (mclk=sdclk) current consumption during cpu running (mclk/sdclk) (mclk=1/2sdclk) ? 1 current consumption in halt mode current consumption in halt mode (operating cloc k=48mhz 1/n) ? 2 (unless otherwise specified: v ddh =3.3v, v dd =1.8v, v ss =0v, ta=25 c) symbol i dd1 i dd2 i dd3 i dd4 max. C C C C C C C C C C C C C C C C C C C C unit ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma condition 20mhz 25mhz 33mhz 48mhz 60mhz 24/48mhz 30/60mhz 40/80mhz 45/90mhz 20mhz 25mhz 33mhz 48mhz 60mhz 1/1 (=48mhz) 1/2 (=24mhz) 1/4 (=12mhz) 1/8 (=6mhz) 1/16 (=3mhz) 1/32 (=1.5mhz) typ. 8.0 10.0 13.0 19.0 23.5 10.0 14.0 20.0 21.0 1.3 1.6 2.1 3.0 4.0 3.0 2.2 1.8 1.6 1.5 1.4 min. C C C C C C C C C C C C C C C C C C C C ? 1 1 1 1 2 1 2 2 2 1 1 1 1 2 3 3 3 3 3 3 current consumption measurement condition: v ih =v ddh , v il =0 v, output pins are open, v dd power current only typ. value measurement condition: v ddh =av dd =3.3 v, v dd =1.8 v, ta=25 c typ. sample ? note) no. 1 2 3 osc3 on on on osc1 off off off cpu normal operation ? 3 normal operation ? 3 halt mode other peripheral circuits stopped pll ( 2) only is used when the osc3 frequency is 30mhz or more. others are stopped. stopped ?1 : the mclk (cpu operating clock) frequency is set to half of the sdclk (sdram clock). ?2 : the operating clock actually used is the mclk divided clock specified with the cmu_clksel regis - ter. the cmu_clksel register can be rewritten anytime necessary, note, however, that a hazard may occur on the clock output when the register is changed. the lower the operating frequency, the lower the current consumption is realized. however, it affects the clock frequency supplied to the peripheral circuits, therefore, it is necessary to control the clock supply (on/off) or to reset the prescaler. ?3 : the values of current consumption while the cpu was operating were measured when a test pro - gram consisting of 55 % load instructions, 23 % arithmetic operation instructions, 1 % mac instruction, 12 % branch instructions and 9 % ext instructions was executed continuously in the built-in rom. current consumption in sleep mode item current consumption in sleep mode (unless otherwise specified: v ddh =3.3v, v dd =1.8v, v ss =0v, ta=25 c) symbol i ds1 i ds2 max. C C unit a a condition 48mhz 32khz (system clock = osc1) typ. 1.0 2.0 min. C C ? current consumption measurement condition: v ih =v ddh , v il =0 v, output pins are open typ. value measurement condition: v ddh =av dd =3.3 v, v dd =1.8 v, ta=25 c typ. sample
i s1c33e08 specifications: electrical characteristics i-7-4 epson s1c33e08 technical manual peripheral circuit operating currents item sram controller operating current sdram controller operating current dma controller operating current lcd controller operating current usb controller operating current rtc operating current osc3 operating current sscg operating current pll operating current a/d converter operating current mp3 decoder operating current (unless otherwise specified: v ddh =av dd =3.3v, v dd =plv dd =1.8v, v ss =0v, ta=25 c) symbol i sr i sd i dma i lcd i usb i rtc i osc3 i sscg i pll i ad i mp 3 max. C C C C C C C C C C C unit ma ma ma ma ma a ma a ma a ma condition when sram clock is supplied. (48mhz) when sdram clock is supplied. (48mhz) when dma clock is supplied. (48mhz) when lcdc clock is supplied. (48mhz ) idle state when usb clock is supplied. (48mhz) osc1 oscillation (32khz) osc3 oscillation (48mhz) sscg input clock (48mhz) pll output clock (90mhz) when a/d converter is enabled when mp3 decoder is on playback typ. 3.4 5.4 3.9 5.3 10.0 2.0 1.3 400.0 2.1 260.0 8.0 min. C C C C C C C C C C C ? 4 4 4 4 4 4 4 4 5 6 7 ? note 4 ) v dd power current consumption in idle status when the clock is supplied 5 ) plv dd power current consumption 6 ) av dd power current consumption 7 ) except on stop or pause state
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.5 a/d converter characteristics item resolution conversion time zero scale error full scale error integral linearity error differential linearity error permissible signal source impedance analog input capacitance (unless otherwise specified: v ddh =av dd =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c, st[1:0]=11) symbol C C e zs e fs e l e d C C max. C 1250 2 2 3 3 5 45 unit bit s lsb lsb lsb lsb k ? pf condition typ. 10 C C C C C C C min. C 10 -2 -2 -3 -3 C C ? 1 ? note 1 ) indicates the minimum value when a/d clock = 2mhz. indicates the maximum value when a/d clock = 16khz. a/d conversion error v[001]h = ideal voltage at zero-scale point (=0.5lsb) v'[001]h = actual voltage at zero-scale point v[3ff]h = ideal voltage at full-scale point (=1022.5lsb) v'[3ff]h = actual voltage at full-scale point 1lsb = 1lsb' = av dd - v ss 2 10 - 1 v'[3ff]h - v'[001]h 2 10 - 2 v'[001]h 3ff 3fe 3fd 003 002 001 000 v ss av dd integral linearity error e l = [lsb] v n ' - v n 1lsb' digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v'[3ff]h v'[n]h v n ' v n v'[n-1]h n+1 n n-1 n-2 integral linearity error differential linearity error differential linearity error e d = - 1 [lsb] v'[n]h - v'[n-1]h 1lsb' digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v[001]h (=0.5lsb) v'[001]h 004 003 002 001 000 v ss zero scale error zero scale error e zs = [lsb] (v'[001]h - 0.5lsb') - (v[001]h - 0.5lsb) 1lsb digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v[3ff]h (=1022.5lsb) v'[3ff]h 3ff 3fe 3fd 3fc 3fb av dd full scale error full scale error e fs = [lsb] (v'[3ff]h + 0.5lsb') - (v[3ff]h + 0.5lsb) 1lsb digital output (hex) analog input ideal conversion characteristic actual conversion characteristic
i s1c33e08 specifications: electrical characteristics i-7-6 epson s1c33e08 technical manual i.7.6 oscillation characteristics oscillation characteristics change depending on conditions such as components used (oscillator, r f , r d , c g , c d ) and board pattern. use the following characteristics as reference values. in particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (r f , r d ) and capacitor (c g , c d ) values are finally decided. osc1 oscillation (crystal) item oscillation start time (unless otherwise specified: v dd =1.65v to 1.95v, v ss =0v, ta=25 c) symbol t sta1 max. 3 unit s condition typ. min. ? osc3 oscillation (crystal/ceramic) note : a crystal resonator that uses a fundamental should be used for the osc3 crystal oscillation circuit. item oscillation start time (unless otherwise specified: v dd =1.70v to 1.90v, v ss =0v, ta=25 c) symbol t sta3 max. 25 unit ms condition typ. min. ?
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.7 pll characteristics item input frequency output frequency output stabilization time (unless otherwise specified: plv dd =1.65v to 1.95v, plv ss =0v, ta=-40 c to +85 c) symbol f pllin f pllout t pll max. 50 90 200 unit mhz mhz s condition typ. min. 5 20 ? 1 2 ? note 1 ) input clock source divider: osc3 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10 2 ) multiplication rate: 1, 2, 4, 8, 10, 15
i s1c33e08 specifications: electrical characteristics i-7-8 epson s1c33e08 technical manual i.7.8 ac characteristics i.7.8.1 symbol description t cyc : bus-clock cycle time indicates the cycle time of the bus clock. i.7.8.2 ac characteristics measurement condition signal detection level: input signal high level v ih = v ddh - 0.4 v low level v il = 0.4 v output signal high level v oh = 1/2 v ddh low level v ol = 1/2 v ddh the following applies when osc 3 is external clock input: input signal high level v ih = 1/2 v dd low level v il = 1/2 v dd input signal waveform: rise time ( 10% 90 % v dd ) 5 ns fall time ( 90% 10 % v dd ) 5 ns output load capacitance: pins other than sdclk: c l = 50 pf sdclk pin: c l = 20 pf
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.8.3 sramc ac characteristic tables external clock input characteristics (note) these ac characteristics apply to input signals from outside the ic. the osc 3 input clock must be within v dd to v ss voltage range. item high-speed clock cycle time osc3 clock input duty osc3 clock input rise time osc3 clock input fall time bclk high-level output delay time bclk low-level output delay time (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c) symbol t c3 t c3ed t if t ir t cd1 t cd2 max. 500 55 5 5 25 25 unit ns % ns ns ns ns min. 16.7 45 ? bclk clock output characteristics (note) these ac characteristic values are applied only when the high-speed oscillation circuit is used. item bclk clock output duty (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c) symbol t cbd max. 60 unit % min. 40 ? bus access cycle item cmu_clk output dela y time address dela y time #ce x dela y time wr ite dela y time wr ite data dela y time wr ite data hold time read dela y time read data setup time read data hold time wr ite signal pulse width read signal pulse width read address access time chip enab le access time read signal access time #w ait setup time #w ait hold time (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, external load=50pf, ta=-40 c to +85 c) symbol t cd t ad t ced t wr d t wrdd t wrdh t rdd t rds t rddh t wr w t rd w t ac c t cea c t rd ac t wt s t wt h max. 20 14 14 14 14 14 t cyc (1+wc)-26 t cyc (1+wc)-26 t cyc (1+wc)-26 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. -2 12 0 t cyc (1+wc)-14 t cyc (1+wc)-14 12 0 ?
i s1c33e08 specifications: electrical characteristics i-7-10 epson s1c33e08 technical manual i.7.8.4 sramc ac characteristic timing charts clock osc3 (high-speed clock) t c3 bclk (clock output) t c3 ( t cyc ) t c3h t c3ed = t c3h / t c3 t cbd = t cbh / t cyc bclk (clock output) t cyc t cbh t cd1 t cd2 t if t ir (1) when an external clock is input: (2) when the high-speed oscillation circuit is used for the operating clock: sram read cycle mclki cmu_clk (p52) a[24:0] #ce x #rd d[15:0] #wait t cd t cyc t ad t ced t rdd t rdd t ad t ced valid valid t rds t rddh t rdw t wt s t wt h sram write cycle mclki cmu_clk (p52) a[24:0] #ce x #wr x d[15:0] #wait t cd t cyc t ad t ced t wr d t wr d t ad t ced valid valid t wrdd t wt s t wrdh t wt h t wr w
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.8.5 sdram interface ac characteristics normal mode (sdclk = mclk, 60mhz max.) item address delay time address hold time sda10 delay time sda10 hold time #sdcs delay time #sdcs hold time #sdras signal delay time #sdras signal hold time #sdcas signal delay time #sdcas signal hold time dqmh, dqml signal delay time dqmh, dqml signal hold time sdcke signal delay time sdcke signal hold time #sdwe signal delay time #sdwe signal hold time read data setup time read data hold time write data delay time write data hold time (unless otherwise specified: v ddh =2.7v to 3.3v, v dd =1.65v to 1.95v, ta=-40 c to +85 c external load conditions: address bus/data bus=50pf, sdclk/control signals=20pf) symbol t ad t ah t a10d t a10h t csd t csh t rasd t rash t casd t cash t dqm d t dqm h t cked t ckeh t we d t we h t rds t rdh t wd d t wd h max. 10 10 10 10 10 10 10 10 11 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4 0 1.5 ? double frequency mode (sdclk = 2 mclk, 90mhz max.) item address delay time address hold time sda10 delay time sda10 hold time #sdcs delay time #sdcs hold time #sdras signal delay time #sdras signal hold time #sdcas signal delay time #sdcas signal hold time dqmh, dqml signal delay time dqmh, dqml signal hold time sdcke signal delay time sdcke signal hold time #sdwe signal delay time #sdwe signal hold time read data setup time read data hold time write data delay time write data hold time (unless otherwise specified: v ddh =2.7v to 3.3v, v dd =1.65v to 1.95v, ta=-40 c to +85 c external load conditions: address bus/data bus=30pf, sdclk/control signals=20pf) symbol t ad t ah t a10d t a10h t csd t csh t rasd t rash t casd t cash t dqm d t dqm h t cked t ckeh t we d t we h t rds t rdh t wd d t wd h max. 8 8 8 8 8 8 8 8 8 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4 0 1.5 ? note : all the signals change at the rising edge of the sdram clock.
i s1c33e08 specifications: electrical characteristics i-7-12 epson s1c33e08 technical manual sdram access cycle (write) (read) (column) (bank, row) bank active (column) t we h t cash sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t ad t ah t a10h read nop h valid valid valid t a10d t csd t csh t we d t we d t wd d t we h t dqm d t wd h t dqmh valid valid valid valid valid valid idle nop write t rasd t rash t casd t rdh t rds ? read: cas latency = 2 , burst length = 2 write: single write sdram mode-register-set cycle t cash sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml mode register set t ad t ah nop nop h valid t a10d t a10h t csd t csh t we d t we h valid nop t rasd t rash t casd
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 sdram auto-refresh cycle sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t cash auto refresh nop nop h t csd t csh t we d t we h nop t rasd t rash t casd ? a precharge cycle is necessary before entering the auto refresh mode. sdram self-refresh cycle sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t csd t csh t we d exit self refresh mode enter self refresh mode t rasd t casd t cked ? a precharge cycle is necessary before entering the self refresh mode.
i s1c33e08 specifications: electrical characteristics i-7-14 epson s1c33e08 technical manual i.7.8.6 lcdc ac characteristics conditions: v ddh = 2.7v to 3.6v ta = - 40 c to 85 c trise and tfall for all outputs should be < 5 ns (10% ~ 90%) c l = 60 pf (lcd panel interface) power up/down timing #reset psave[1:0] bits (d[1:0]/0x301a04) fp signals lcd power active inactive inactive t 1 t 4 t 3 t 2 11 00 00 symbol t 1 t 2 t 3 t 4 max. 1 1 unit frame frame frame frame parameter power save inactive to fpline, fpframe, fpshift, fpdat, fpdrdy active fpline, fpframe, fpshift, fpdat, fpdrdy active to lcd power on power save active to lcd power off power save active to fpline, fpframe, fpshift, fpdat, fpdrdy inactive typ. min. 1 1 note) any i/o port can be used for controlling the power supply to the lcd panel. note, however, that the t 2 and t 3 timing conditions must be satisfied when controlling the signal.
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-15 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 4 -bit single monochrome panel timing fpframe fpline fpdrdy (mod) fpdat[7:4] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 line 1 1-1 1-5 1-317 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel for this timing diagram fpsmask (d 29/0x301a60) is set to 1 vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-16 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:4] data timing note : for this timing diagram fpsmask (d29/0x301a60) is set to 1. 4 -bit single monochrome panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:4] setup to shift pulse falling edge fpdat[7:4] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +2 4 2 2 2 2 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 2 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-17 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8 -bit single monochrome panel timing fpframe fpline fpdrdy (mod) fpdat[7:0] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-1 1-9 1-313 1-2 1-10 1-314 1-3 1-11 1-315 1-4 1-12 1-316 1-5 1-13 1-317 1-6 1-14 1-318 1-7 1-15 1-319 1-8 1-16 1-320 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel for this timing diagram fpsmask (d 29/0x301a60) is set to 1 vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-18 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:0] data timing note : for this timing diagram fpsmask (d29/0x301a60) is set to 1. 8 -bit single monochrome panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:0] setup to shift pulse falling edge fpdat[7:0] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +4 8 4 4 4 4 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 4 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 13 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-19 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 4-bit single color panel timing fpframe fpline fpdrdy (mod) fpdat[7:4] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 line 1 1-r1 1-g2 1-b31 9 1-g1 1-b2 1-r320 1-b1 1-r3 1-g320 1-r2 1-g3 1-b3 1-r4 1-g4 1-b4 1-b32 0 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-20 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:4] data timing 4 -bit single color panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:4] setup to shift pulse falling edge fpdat[7:4] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +0.5 1 0.5 0.5 0.5 0.5 23 (24) note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 1.5 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 10.5 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-21 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8-bit single color panel timing (format 1) fpframe fpline fpdat[7:0] vdp vndp fpline fpshift fpshift2 fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-r1 1-g1 1-r236 1-b1 1-r2 1-b23 6 1-g2 1-b2 1-g237 1-r3 1-g3 1-r238 1-b3 1-r4 1-b23 8 1-g4 1-b4 1-g239 1-r5 1-g5 1-r240 1-b5 1-r6 1-b24 0 1-g6 1-r7 1-b7 1-g8 1-r9 1-b9 1-g10 1-r11 1-b6 1-g7 1-r8 1-b8 1-g9 1-r10 1-b10 1-g11 1-b11 1-g12 1-r13 1-b13 1-g14 1-r15 1-b15 1-g16 1-r12 1-b12 1-g13 1-r14 1-b14 1-g15 1-r16 1-b16 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-22 epson s1c33e08 technical manual frame pulse line pulse sync timing t 2 t 1 t 6b t 6a t 8 t 9 t 7a t 7b t 14 t 11 t 10 t 12 t 13 t 12 t 13 t 4 t 3 line pulse shift pulse 2 shift pulse fpdat[7:0] data timing 1 2 8 -bit single color panel ac timing (format 1) symbol t 1 t 2 t 3 t 4 t 6a t 6b t 7a t 7b t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width shift pulse falling edge to line pulse rising edge shift pulse 2 falling edge to line pulse rising edge shift pulse 2 falling edge to line pulse falling edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse rising, shift pulse 2 falling edge shift pulse 2, shift pulse period shift pulse 2, shift pulse width low shift pulse 2, shift pulse width high fpdat[7:0] setup to shift pulse 2, shift pulse falling edge fpdat[7:0] hold from shift pulse 2, shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 note 4 note 5 note 6 note 7 t 14 +2 4 2 2 1 1 23 (25) note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + t 13 - t 10 + 1 (ts) 5 . t 6bmin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + t 13 + 1 (ts) 6 . t 7amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 (ts) 7 . t 7amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 - t 10 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-23 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8-bit single color panel timing (format 2) fpframe fpline fpdrdy (mod) fpdat[7:0] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-r1 1-b3 1-g238 1-g1 1-r4 1-b23 8 1-b1 1-g4 1-r239 1-r2 1-b4 1-g239 1-g2 1-r5 1-b23 9 1-b2 1-g5 1-r240 1-r3 1-b5 1-g240 1-g3 1-r6 1-g6 1-b6 1-r7 1-g7 1-b7 1-r8 1-g8 1-b8 1-b24 0 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-24 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:0] data timing 8 -bit single color panel ac timing (format 2) symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:0] setup to shift pulse falling edge fpdat[7:0] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +2 2 (3) 1 1 1 1 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 1 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 10 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-25 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 12 -bit generic hr-tft panel timing (1 ) generic hr-tft panel horizontal timing d1 d2 d3 d319 d320 fpframe (sps) fpline (lp) fpline (lp) fpshift (clk) fpdat[11:0] tft_ctl3 (spl) tft_ctl1 (cls) tft_ctl0 (ps) tft_ctl2 (rev) t 7 t 5 t 3 t 2 t 1 t 9 t 4 t 6 t 8 ? example timing for a 320 240 panel symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 max. 440 unit (note 1) ts ts ts ts ts ts ts ts parameter fpline start position total horizontal period fpline width fpshift period horizontal display start position horizontal display period fpline rising edge to tft_ctl3 rising edge tft_ctl3 pulse width fpline rising edge to tft_ctl2 change typ. note 2 note 3 note 4 1 note 5 note 6 59 1 11 min. 400 note) 1 . ts = pixel clock period 2 . t 1typ = fplst[ 9:0] + 1 (ts) fplst[9:0] (d[25:16]/0x301a28) 3 . t 2typ = (htcnt[ 6:0] + 1) 8 (ts) htcnt[6:0] (d[22:16]/0x301a10) 4 . t 3typ = fplwd[ 6:0] + 1 (ts) fplwd[ 6:0] (d[6:0]/0x301a28) 5 . t 5typ = hdpscnt[ 9:0] + 1 (ts) hdpscnt[9:0] (d[9:0]/0x301a20) 6 . t 6typ = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[6:0] (d[6:0]/0x301a10) (2 ) generic hr-tft panel vertical timing line 1 line 2 line 239 line 240 fpdat[11:0] fpframe (sps) t 2 t 4 t 3 t 1 ? example timing for a 320 240 panel symbol t 1 t 2 t 3 t 4 max. 330 unit lines lines lines lines parameter total vertical period vertical display start position vertical display period vertical sync pulse width typ. note 1 note 2 note 3 2 min. 245 note) 1 . t 1typ = vtcnt[ 9:0] + 1 (lines) vtcnt[9:0] (d[25:16]/0x301a14) 2 . t 2typ = vdpscnt[ 9:0 ] (lines) vdpscnt[9:0] (d[9:0]/0x301a24) 3 . t 3typ = vdpcnt[ 9:0] + 1 (lines) vdpcnt[9:0] (d[9:0]/0x301a14)
i s1c33e08 specifications: electrical characteristics i-7-26 epson s1c33e08 technical manual (3 ) generic hr-tft panel control signal offset timings fpline (lp) tft_ctl1 (cls) tft_ctl0 (ps) tft_ctl2 (rev) stop0 delay start1 stop1 start0 ? when fplst[9:0] (d[25:16]/0x301a28) = 0x0 start 1 = ctl1st[7:0] (ts) ctl1st[7:0] (d[7:0]/0x301a44) stop 1 = ctl1stp[7:0] + 1 (ts) ctl1stp[7:0] (d[23:16]/0x301a44) start 0 = ctl0st[7:0] (ts) ctl0st[7:0] (d[7:0]/0x301a48) stop 0 = ctl0stp[7:0] + 1 (ts) ctl0stp[7:0] (d[23:16]/0x301a48) delay = ctl 2 dly[7:0] (ts) ctl2 dly[7:0] (d[7:0]/0x301a4c)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-27 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.9 usb dc and ac characteristics input levels item vbus input high (driven) high (floating) low differential input sensitivity differential common mode range (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol v bus v ih v ihz v il v di v cm max. 5.25 C 3.6 0.8 C 2.5 unit v v v v v v condition |dp - dm| include v di range typ. C C C C C C min. 4.40 2.0 2.7 C 0.2 0.8 ? 1 2 2 2 ? note 1 ) refer to section 7.2.1 in the usb2.0 specification for the conditions. 2 ) refer to section 7.1.4 in the usb2.0 specification for the conditions. output levels item low high (driven) output signal crossover voltage (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol v ol v oh v crs max. 0.3 3.6 2.0 unit v v v condition typ. C C C min. 0.0 2.8 1.3 ? 3 3 4 ? note 3 ) refer to section 7.1.1 in the usb2.0 specification for the conditions. 4 ) refer to figures 7-8 and 7-9 in the usb2.0 specification for the conditions. terminations item bus pull-up resistor on upstream facing port (idle bus) bus pull-up resistor on upstream facing port (receiving) (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol r pui v pua max. 1.575 3.090 unit k ? k ? condition typ. C C min. 0.9 1.425 ? 5 5 ? note 5 ) refer to ecn in the usb2.0 specification for the conditions. driver characteristics max. 20 20 111.11 44 typ. C C C C C min. 4 4 90 28 125 item rise time fall time differential rise and fall time matching driver output resistance vbus input impedance vbus resistor ratio (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol t fr t ff t frfm z drv z vbus unit ns ns % ? k ? condition t fr /t ff r1 + r2 r1 : r2 1 : 2 (nominal) ? 4 4 ? note 4 ) refer to figures 7-8 and 7-9 in the usb2.0 specification for the conditions.
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i s1c33e08 specifications: basic external wiring diagram s1c33e08 technical manual epson i-8-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.8 basic external wiring diagram x'tal1 c g1 c d1 rf 1 rd 1 crystal resonator gate capacitor drain capacitor feedback resistor drain resistor 32.768 khz 12 pf ? 4 12 pf ? 4 10 m ? ? 4 0 ? ? 4 x'tal2 or ce c g2 c d2 rf 2 rd 2 resonator gate capacitor drain capacitor feedback resistor drain resistor crystal 3 pf 4 pf 1 m ? 0 ? ceramic ? 1 (6 pf) (6 pf) 22 k ? 47 ? note : ? 1 cstcw48m0x11 ??? ? 2 oscillation characteristics vary depending on conditions (components used, board pattern, etc.). the values in the above table are shown only for reference and not guaranteed. in particular, ceramic oscillation is extremely sensitive to influence of external components and printed-circuit boards. before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. furthermore, this chip supports only 48-mhz ceramic resonators. do not use ceramic resonators with any other frequency. ? 3 capacitance built into the ceramic resonator ? 4 oscillation characteristics vary depending on conditions (components used, board pattern, etc.). the values in the above table are shown only for reference and not guaranteed. ? 2, ? 3 ? 2, ? 3 ? 2 ? 2 s1c33e08 [the potential of the substrate (back of the chip) is v ss .] external bus hsdma a[24:1], a0/#bsl d[15:0] #rd #wrl #wrh/#bsh #cexx #wait bclk #nmi cmu_clk wdt_clk #wdt_nmi sdclk sdcke sda10 dqmh dqml #sdcs #sdras #sdcas #sdwe #dmareqx #dmaackx #dmaendx fpframe fpline fpdat[11:0] fpshift fpdrdy tft_ctl[3:0] usbdp usbdm usbvbus sinx soutx #sclkx #srdyx sdi sdo spi_clk dcsio0 dcsio1 #smrd #smwr #iord #iowr #oe #we #cfce1 #cfce2 i2s_sdo i2s_ws i2s_scl i2s_mclk #adtrg ainx exclx tmx pxx sdram lcd panel card i 2 s a/d input timer input/output i/o usb spi dcsio serial i/o debug interface v dd plv dd v ddh av dd boot1 boot0 mclki mclko rtc_clki rtc_clko #reset vcp test0 burnin v ss dst[2:0] dpco dclk dsio 1.8 v 3.0/3.3 v rd 2 rd 1 c d2 x'tal2 or ce rf 2 c g2 c d1 x'tal1 rf 1 c g1 + +
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i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.9 precautions on mounting the following shows the precautions when designing the board and mounting the ic. oscillation circuit ? oscillation characteristics change depending on conditions such as components used (oscillator, r f , r d , c g , c d ) and board pattern. in particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (r f , r d ) and capacitor (c g , c d ) values are finally decided. ? disturbances of the oscillation clock due to noise may cause a malfunction. to prevent this, the following points should be taken into consideration. in particular, the latest devices are more sensitive to noise, as they are more finely processed. the measures against noise for the rtc_clko pin, and the components and lines connected to this pin is most essential, and similar measures must also be taken for the rtc_clki pin. the measures for the rtc_clki and rtc_clko pins are described below. we recommend taking measures similar to those for the high-speed oscillation system, including the mclki and mclko pins and the components and lines connected to these pins. (1 ) components that are connected to the rtc_clki and rtc_clko pins, such as oscillators, resistors, and capacitors, should be connected in the shortest line. (2 ) whenever possible, configure digital signal lines with at least three millimeters clearance from the rtc_clki and rtc_clko pins and the components and lines connected to these pins. in particular, signals that are switched frequently must not be placed near these pins, components, and lines. the same applies to all layers on the multi-layered board as the distance between the layers is around 0.1 to 0.2 mm. furthermore, do not configure digital signal lines in parallel with these components and lines when arranging them on the same or another layer of the board. such an arrangement is strictly prohibited, even with clearance of three millimeters or more. also, avoid arranging digital signal lines across these components and signal lines. (3 ) shield the rtc_clki and rtc_clko pins and lines connected to those pins as well as the adjacent layers of the board using v ss . as shown in the figure on the right, shield the wired layers as much as possible. whenever possible, make the whole adjacent layers the ground layers, or ensure there is adequate shielding to a radius of five millimeters around the above pins and lines. as described in ( 2 ), do not configure digital signal lines in parallel with components and lines even if such precautionary measures are taken, and avoid configuring signal lines that are switched frequently across components and lines on other layers. (4 ) when an external clock is supplied to the rtc_clki or mclki pin, the clock source should be connected to the rtc_clki or mclki pin in the shortest line. furthermore, do not connect anything else to the rtc_clko or mclko pin. (5 ) after taking the above precautions, check the output clock waveform while operating the actual application program in the actual device. to do this, measure the output of the cmu_clk pins with an oscilloscope. check the waveform quality at the osc 3 or pll output clock by measuring the cmu_clk output. ensure that the frequencies are as designed and that there is no noise or jitters. check the waveform quality at the osc 1 clock by measuring the cmu_clk output (after switching the system clock source to osc 1 ). scale up the ranges around the rising and falling edges of the clock pulse to ensure that there is no noise, such as clock and spike, in the 100 ns ranges. rtc_clki rtc_clko v ss sample v ss pattern rtc_clki and rtc_clko
i s1c33e08 specifications: precautions on mounting i-9-2 epson s1c33e08 technical manual if conditions ( 1 ) to (3 ) are not satisfied, the osc3 or pll output may be jittery and the osc1 output may be noisy. when the osc 3 or pll output is jittery, the operating frequency will be lowered. when the osc1 output is noisy, operation of the rtc using the osc 1 clock and the cpu core after the system clock is switched to osc1 will be unstable. reset circuit ? the power-on reset signal which is input to the #reset pin changes depending on conditions (power rise time, components used, board pattern, etc.). decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. ? in order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the #reset pin in the shortest line. power supply circuit ? sudden power supply variation due to noise may cause malfunction. consider the following points to prevent this: (1 ) the power supply should be connected to the v dd , v ddh , v ss , av dd , plv dd and plv ss pins with patterns as short and large as possible. in particular, the power supply for av dd affects a/d conversion precision. (2 ) when connecting between the v dd and v ss pins with a bypass capacitor, the pins should be connected as short as possible. v dd v ss bypass capacitor connection example v dd v ss a/d converter ? when the a/d converter is not used, the power supply pin av dd for the analog system should be connected to v ddh . arrangement of signal lines ? in order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. ? when a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. do not arrange a high- speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. p70 (ain0) large current signal line high-speed signal line large current signal line high-speed signal line prohibited pattern rtc_clko, mclko rtc_clki, mclki v ss
i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 usb the i/o block of the usb function controller incorporated in t his chip has the following features: the dp and dm pins can be connected directly to the usb connect or. the vbus level is detected by means of a 2/3 resistive division internally in the chip, thus allowing for direct input of a 5 v-level signal. the receiver does not enter a floating state even when the usb cable is disconnected from the usb connector. when the usb cable is disconnected, the vbus pin is tied to v ss , so that leakage current will be the only source that drains power in the usb i/o block. precautions on vbus be sure to not apply 6 v (max.) or more to the vbus pin as the ic may be destroyed. it is especially necessary to suppress overshoot on the input voltage and to prevent the host power source becoming unstable when the usb cable is plugged into the connector. to do this, connect a 1 f or more capacitor near the usb connector for decoupling the vbus signal. choose a ceramic capacitor for decoupling. usb connector vbus pin usbvbus pin 1 f or more in addition to the above, verify the vbus state completely on the actual circuit board using an oscilloscope or other device. overshoot and other symptoms are more likely to occur when using a long usb cable and connecting it to the host side connector. precautions on dp and dm when designing a printed circuit board, observe the following precautions to ensure that both dp and dm signals are properly routed: ? to prevent signal skew and to stabilize differential impedance, the dp and dm signal lines must be routed in parallel and in the same length, with the pins and connector connected in the shortest distance possible. crossed wiring of these signals should be avoided as much as possible. ? the periphery of these signal lines must be enclosed by a gnd pattern, and with the gnd pattern also created for the internal layer immediately below that. in particular, the routing of high-speed digital signal lines parallel to or across these signal lines should be avoided as much as possible. we recommend that you verify the eye pattern on the actual circuit board. sample eye diagram
i s1c33e08 specifications: precautions on mounting i-9-4 epson s1c33e08 technical manual noise-induced erratic operations if erratic ic operations appear to be attributable to noise, consider the following five points. ( 1 ) test0 pin if this pin is exposed to high-level noise, the entire ic enters test mode or a high-impedance state and becomes inoperable. in such cases, the ic will not be restored, even when the pin is returned to a low level. therefore, always make sure the test 0 pin is connected to gnd on the circuit board. although the ic contains internal pull-down resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k ? ). ( 2 ) dsio pin exposure of this pin to low-level noise causes the ic to enter debug mode. in debug mode, the clock is output from the dclk pin and the dst2 pin is high, indicating that the ic is in debug mode. in product versions, it is recommended that the dsio pin be pulled high by connecting it directly to v dd or through a resistor of 10 k ? or less. although the ic contains internal pull-up resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k ?). for details, refer to the s1c33 family application note. ( 3 ) #reset pin low-level noise on this pin resets the ic. however, the ic may not always be reset normally, depending on the input waveform. due to circuit design, this situation tends to occur when the reset input is in the high state, with high impedance. for details, refer to the s1c33 family application note. ( 4 ) #nmi pin low-level noise on this pin causes an nmi interrupt. due to the circuit design, this situation tends to occur when the #nmi pin is in the high state, with high impedance. lower the impedance of #nmi when it is held high, or incorporate corrective measures into the software to protect against erratic operations. ( 5 ) v dd , v ss , and v ddh power supplies if noise lower than the rated voltage enters one of these power-supply lines, the ic may operate erratically. take corrective measures in board design; for example, by using solid patterns for power supply lines, adding decoupling capacitors to eliminate noise, or incorporating surge/noise counteracting devices into the power supply lines. to confirm the above, use an oscilloscope capable of observing higher-frequency waveforms of 200 mhz. the generation of fast noise may not be observed with a low-frequency oscilloscope. if potential noise-induced erratic operations are detected through waveform observations using an oscilloscope, connect the suspected pin to the gnd or power supply with low impedance ( 1 k ? or less) and check once again. if erratic operations are no longer detected or occur at reduced frequency, or if different symptoms of erratic operations are observed, said pin may with reasonably certainty be considered to be the source of the erratic operations. the test 0 , dsio, #reset, and #nmi input circuits described above are designed to detect the edges of the input signal (#nmi can be changed to level sense mode), so that even spike noise may result in erratic operations. among the digital signal circuits, these pins are most susceptible to noise. in the design of the circuit board, take the following two points into consideration to protect the signal from noise. (a) the most important measure is to lower the signal-driving impedance, as described in each item above. connect pins to the power supply or gnd, with impedance of 1 k ? or less, preferably 0 ? . in addition, limit the length of the connected signal lines to approximately 5 cm. (b) parallel routing of said signal lines with other digital lines on the board is undesirable, since the noise generated when the signal changes from high to low or vice versa may adversely affect signals. the signal may be subject to the most noise when signal lines are laid between multiple signal lines whose states change simultaneously. take corrective measures by shortening the parallel distance (to several cm) or separating signal lines (2 mm or more).
i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 reference refer to chapter 4, the basic s1c33 chip board circuit, in the s1c33 family application note for more detailed precautions on the power supply, oscillation, reset, memory, port, and debug. other the 0.18 m fine-pattern process is employed to manufacture this series of products. although the product is designed to meet eiaj and mil standards regarding basic ic reliability, please pay careful attention to the following points when actually mounting the chip on a board. since all the oscillator input/output pins are constructed to use the internal 0.18 m transistors directly, the pins are susceptible to mechanical damage during the board-mounting process. moreover, the pins may also be susceptible to electrical damage caused by such disturbances (listed below) whose electrical strength, varying gradually with time, could exceed the absolute maximum rated voltage ( 2.5 v) of the ic: (1 ) electromagnetic induction noise from the utility power supply in the reflow process during board-mounting, rework process after board-mounting, or individual characteristic evaluation (experimental confirmation), and (2 ) electromagnetic induction noise from the tip of a soldering ir on especially when using a soldering iron, make sure that the ic gnd and soldering iron gnd are at the same potential before soldering.
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual ii bus modules
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1 high-speed dma (hsdma) ii.1.1 functional outline of hsdma the s 1c33e08 contains four channels of hsdma (high-speed dma) circuits that support dual-address transfer and single-address transfer methods. since the control registers required for the hsdma function are implemented with logic circuits (not located in a memory), hsdma requests for data transfer can respond to insta ntaneously. notes : ? channels 0 to 3 are configured in the same way and have the same functionality. signal and control bit names are assigned channel numbers 0 to 3 to distinguish them from other chan - nels. in this manual, however, channel numbers 0 to 3 are designated with an x except where they must be distinguished, as the explanation is the same for all channels. ? the mp3 decoder bios (mp3 decoder module) uses hsdma ch.0 and ch.1 , therefore, these two channels cannot be used while the mp 3 decoder is active. dual-address transfer in this method, a source address and a destination address for dma transfer can be specified and a dma trans - fer is performed in two phases. the first phase reads data at the source address into the on-chip temporary reg - ister. the second phase writes the temporary register data to the destination address. unlike idma (intelligent dma), which has transfer information in memory, this dma method does not sup - port a dma link function but allows high-speed data transfers because it is not necessary to read transfer infor - mation from a memory. memory, i/o data transfer (1) (1) transfer data is read from the source memory or i/o device. (2) transfer data is written to the destination memory or i/o device. (2) destination memory, i/o source hsdma ch.0 ch.1 ch.2 ch.3 itc end of dma dma acknowledge dma request #dmareq x sramc/ sdramc #dmaend x #dmaack x address bus cpu-ahb bus dma data transfer request signal transfer count end signal dma data transfer acknowledge signal hardware/software trigger data bus figure ii.1.1.1 dual-address transfer method the features of dual-address transfer are outlined below. ? source external memory and internal memory except areas 0 and 1 ? destination external memory and internal memory except areas 0 and 1 ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (external trigger input, causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? #dmaend output goes low at the last access of data transfer by each trigger. ? #dmaack output goes low when a dma request is accepted.
ii bus modules: high-speed dma (hsdma) ii-1-2 epson s1c33e08 technical manual note : a0ram (area 0), specific rom (area 1), and ivram (area 0) cannot be specified as the source or destination for dma transfer. while ivram (area 3), dst ram (area 3), and the internal pe - ripheral i/o registers (area 6) can be used for dual-address transfer. timing chart of dual-address mode ( 1) sram address #ce (src) #ce (dst) #rd #wr ? #dmaack #dmaend source address read cycle write cycle destination address figure ii.1.1.2 #dmaack/#dmaend signal output timing (sram, standard settings) ( 2) sdram sdclk address #sdcs (src) #sdcs (dst) #sdras #sdcas #sd we #dmaa ck #dmaend ras cas read cycle wr ite cycle ras cas a ctv read a ctv writ figure ii.1.1.3 #dmaack/#dmaend signal output timing (sdram, standard settings) note : two or more access cycles are generated when the device size of the external memory is smaller than the transfer data size. in this case, the #dmaack/#dmaend signal is asserted over these cycles.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 single-address transfer in this method, data transfers that are normally accomplished by executing data read and write operations back- to-back are executed on the external bus collectively at one time, thus further speeding up the transfer opera - tion. the #dmaack x and #dmaend x signals are used to control data transfer. unlike dual-address transfer, this method does not allow memory to memory data transfer but data transfers can be performed in minimum cycles. external i/o #rd/#wr data transfer external memory or external i/o hsdma ch.0 ch.1 ch.2 ch.3 itc end of dma dma acknowledge dma request #dmareq x sramc #dmaend x #dmaack x address bus cpu-ahb bus dma data transfer request signal transfer count end signal bus control signals dma data transfer acknowledge signal hardware/software trigger data bus figure ii.1.1.4 single-address transfer method the features of single-address transfer are outlined below. ? source/destination 1 . between an external i/o and an external memory (except sdram) 2 . between an external i/o and another external i/o ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (external trigger input, causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? #dmaend output goes low at the last access of data transfer by each trigger. ? #dmaack output output for accessing the external i/o in every cycle during transfer. notes : ? a 0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for single-address transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram.
ii bus modules: high-speed dma (hsdma) ii-1-4 epson s1c33e08 technical manual timing chart of single-address mode ( 1) sram address #ce #rd #wr ? #dmaack #dmaend memory address read/write cycle figure ii.1.1.5 #dmaack/#dmaend signal output timing (sram, standard settings) ( 2) sdram the single-address mode does not support sdram.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.2 i/o pins of hsdma table ii. 1.2.1 lists the i/o pins used for hsdma. table ii. 1.2.1 i/o pins of hsdma pin name #dmareq0 #dmareq1 #dmareq2 #dmareq3 #dmaa ck0 #dmaa ck1 #dmaa ck2 #dmaa ck3 #dmaend0 #dmaend1 #dmaend2 #dmaend3 i/o i i i i o o o o o o o o function dma transf er request input pin f or hsdma ch.0 dma transf er request input pin f or hsdma ch.1 dma transf er request input pin f or hsdma ch.2 dma transf er request input pin f or hsdma ch.3 dma ac kno wledge signal output pin f or hsdma ch.0 dma ac kno wledge signal output pin f or hsdma ch.1 dma ac kno wledge signal output pin f or hsdma ch.2 dma ac kno wledge signal output pin f or hsdma ch.3 end-of-transf er signal output pin f or hsdma ch.0 end-of-transf er signal output pin f or hsdma ch.1 end-of-transf er signal output pin f or hsdma ch.2 end-of-transf er signal output pin f or hsdma ch.3 #dmareq x (dma request input pin) this pin is used to input a dma request signal from an external peripheral circuit. one data transfer opera - tion is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). the #dmareq0 to #dmareq3 pins correspond to channel 0 to channel 3 , respectively. in addition to this external input, software trigger or a cause of interrupt can be selected for the hsdma trigger source using the register in the interrupt controller. #dmaack x (dma acknowledge signal output pin) this signal is output to indicate that a dma request has been a cknowledged by the dma controller. in single-address mode, the i/o device that is the source or destination of transfer outputs data to the external bus or takes in data from the external data synchronously with this signal. the #dmaack 0 to #dmaack3 pins correspond to channel 0 to channel 3 , respectively. this signal is also output in dual-address mode. see figures ii. 1.1.2, ii.1.1.3 and ii.1.1.5 for the waveform of the #dmaack x signal. #dmaend x (end-of-transfer signal output pin) this signal is output to indicate that the number of data transfer operations that is set in the control register have been completed. the #dmaend 0 to #dmaend3 pins correspond to channel 0 to channel 3 , respectively. note : the control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the hsdma. be - fore the hsdma signals assigned to these pins can be used, the functions of these pins must be switched for the hsdma by setting each corresponding port function select register. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions.
ii bus modules: high-speed dma (hsdma) ii-1-6 epson s1c33e08 technical manual ii.1.3 programming control information the hsdma operates according to the control information set i n the registers. note that some control bits change their functions according to the address mode. the following explains how to set the contents of control information. before using hsdma, make each the set - tings described below. ii.1.3.1 standard mode and advanced mode the hsdma in the s 1c33e08 is extended from that of the c33 std models. the s1c33e08 hsdma has two operating modes, the standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table ii. 1.3.1.1 shows differences between standard mode and advanced mode. table ii. 1.3.1.1 differences between standard mode and advanced mode function source/destination address bit width w ord (32-bit) data transf er address decrement function with initialization ad v anced mode 32 bits available available standar d mode 28 bits unavailable unavailable to configure the hsdma in advanced mode, set hsdmaadv (d 0/0x30119 c) to 1 . the control registers (0x301162C0x30119 a) for the extended functions are enabled to write after this setting. at initial reset, hsd - maadv (d 0/0x30119c) is set to 0 and the hsdma enters standard mode. ? hsdmaadv : standard/advanced mode select bit in the hsdma std/adv mode select register (d0/0x30119c) the following descriptions unless otherwise specified are common contents for both modes. the extended func - tions in advanced mode are explained assuming that hsdmaadv (d 0/0x30119c) has been set to 1. notes : ? be sure to use the control registers for advanced mode when the hsdma is set to advanced mode. ? the standard or advanced mode currently set is applied to all the hsdma channels. it cannot be selected for each channel individually.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.3.2 sequential access time for idma and hsdma the dmac (idma and hsdma) has a higher priority for use of the ahb bus than the cpu, therefore the cpu must wait for use of the ahb bus while a dma transfer is in progress until it has completed in default settings. furthermore, the lcdc will be unable to read display data from the sdram if a dma transfer between sdram addresses starts. to avoid a problem, such as degradation in graphics performance, caused by dma, a dma trans - fer that exceeds a specified number of cycles (or sequential access time) can be temporarily suspended to release the bus ownership to the cpu or lcdc. the sequential access time can be set to unlimited or 64 to 940 cycles (in 64 mclk cycle increments) using dmaacctime[3:0] (d[3:0]/0x30119e). ? dmaacctime[3:0] : idma and hsdma sequential access time setup bits in the dma sequential access time register (d[3:0]/0x30119e) table ii. 1.3.2.1 setting the sequential access time dmaa cctime3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 dma sequential access time 960 cycles 896 cycles 832 cycles 768 cycles 704 cycles 640 cycles 576 cycles 512 cycles 448 cycles 384 cycles 320 cycles 256 cycles 192 cycles 128 cycles 64 cycles unlimited dmaa cctime2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 dmaa cctime1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 dmaa cctime0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = unlimited) when unlimited is selected, the ahb bus will not be released until a dma transfer has been completed after it starts. specifying a number of cycles allows a dma transfer to be temporarily suspended when the specified cycles of data transfer have been executed to release the bus. the cpu or lcdc can perform a bus access during the sus - pended status. after that, the dmac resumes the data transfer that was being suspended.
ii bus modules: high-speed dma (hsdma) ii-1-8 epson s1c33e08 technical manual ii.1.3.3 setting the registers in dual-address mode make sure that the hsdma channel is disabled (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before setting the control information. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) address mode the address mode select bit dualm x (d15/0x301122 + 0x10? x ) should be set to 1 (dual-address mode). this bit is set to 0 (single-address mode) at initial reset. ? dualm x : ch. x address mode select bit in the hsdma ch. x control register (d15/0x301122 + 0x10? x ) transfer mode a transfer mode should be set using d xmod[1:0] (d[15:14]/0x30112a + 0x10? x). ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) the following three transfer modes are available: single transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 00 , default) in this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the specified size. if data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. successive transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 01) in this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 each time data is transferred. block transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 10) in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. transfer data size standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) datsize x (d14/0x301126 + 0x10? x) is used to set the unit size of data to be transferred. a half-word size ( 16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, wordsize x (d0/0x301162 + 0x10? x ) is provided to select word size (32 bits) in addition to half-word size and byte size that can be selected using datsize x (d14/0x301126 + 0x10? x). ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) table ii. 1.3.3.1 transfer data size selectable in advanced mode w ordsize x 1 0 0 t ransfer data siz e word (32 bits) half-word (16 bits) byte (8 bits) da tsize x x 1 0
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block length when using block transfer mode (d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) = 10 ), the data block length (in units of the selected transfer data size) should be set using blklen x[7:0] (d[7:0]/0x301120 + 0x10? x). ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) note : when performing data transfer in block transfer mode, the block size must not be set to 0. in single transfer and successive transfer modes, blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ) is used as bits 7C 0 of the transfer counter. transfer counter block transfer mode in block transfer mode, up to 16 bits of transfer count can be specified using tc x_l[7:0 ] (d[15:8]/0x301120 + 0x10? x ) and tc x_h[7:0] (d[7:0]/0x301122 + 0x10? x). ? tc x _l[7:0] : ch. x transfer counter [7:0] bits in the hsdma ch. x transfer counter register (d[15:8]/0x301120 + 0x10? x ) ? tc x _h[7:0] : ch. x transfer counter [15:8] bits in the hsdma ch. x control register (d[7:0]/0x301122 + 0x10? x ) single transfer and successive transfer modes in single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using blklen x [7:0 ] (d[7:0 ]/0x301120 + 0x10? x ), tc x _l[ 7:0 ] (d[15:8 ]/0x301120 + 0x10? x ) and tc x _h[ 7:0] (d[7:0]/0x301122 + 0x10? x ). note : the transfer count thus set is decremented according to the transfers performed. if the transfer count is set to 0, it is decremented to all fs by the first transfer performed. this means that you have set the maximum value that is determined by the number of bits available. source and destination addresses standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) in standard mode, a 28 -bit source address and a 28 -bit destination address for dma transfer can be speci - fied using s x adrl[ 15:0 ] (d[15:0 ]/0x301124 + 0x10 ? x ), s x adrh[ 11:0 ] (d[11:0 ]/0x301126 + 0x10 ? x ), d xadrl[15:0] (d[15:0]/0x301128 + 0x10? x) and d xadrh[11:0] (d[11:0]/0x30112a + 0x10? x). ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (d[15:0]/0x301124 + 0x10? x ) ? s x adrh[11:0] : ch. x source address[27:16] in the hsdma ch. x high-order source address setup register (d[11:0]/0x301126 + 0x10? x ) ? d x adrl[15:0] : ch. x destination address[15:0] in the hsdma ch. x low-order destination address setup register (d[15:0]/0x301128 + 0x10? x ) ? d x adrh[11:0] : ch. x destination address[27:16] in the hsdma ch. x high-order destination address setup register (d[11:0]/0x30112a + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, a 32 -bit source address and a 32 -bit destination address for dma transfer can be speci - fied using s x adrl[ 15:0 ] (d[15:0 ]/0x301164 + 0x10 ? x ), s x adrh[ 15:0 ] (d[15:0 ]/0x301166 + 0x10 ? x ), d xadrl[15:0] (d[15:0]/0x301168 + 0x10? x) and d xadrh[15:0] (d[15:0]/0x30116a + 0x10? x). ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register for adv mode (d[15:0]/0x301164 + 0x10? x ) ? s x adrh[15:0] : ch. x source address[31:16] in the hsdma ch. x high-order source address setup register for adv mode (d[15:0]/0x301166 + 0x10? x ) ? d x adrl[15:0] : ch. x destination address[15:0] in the hsdma ch. x low-order destination address setup register for adv mode (d[15:0]/0x301168 + 0x10? x ) ? d x adrh[15:0] : ch. x destination address[31:16] in the hsdma ch. x high-order destination address setup register for adv mode (d[15:0]/0x30116a + 0x10? x ) note : in advanced mode, be sure to use the control registers for advanced mode to set source/destina - tion addresses.
ii bus modules: high-speed dma (hsdma) ii-1-10 epson s1c33e08 technical manual address increment/decrement control standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) the source and/or destination addresses can be incremented or decremented when one data transfer is complet - ed. s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x ) (for source address) and d xin[1:0 ] (d[13:12]/0x30112 a + 0x10? x) (for destination address) are used to set this function. ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? d x in[1:0] : ch. x destination address control bits in the hsdma ch. x high-order destination address setup register (d[13:12]/0x30112a + 0x10? x ) s xin[1:0]/d xin[1:0] = 00 : address fixed (default) the address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read/write from/to the same address. s xin[1:0]/d xin[1:0] = 01 : address decremented without initialization the address is decremented by an amount equal to the specified data size when one data transfer is com - pleted. the address that has been decremented during transfer does not return to the initial value. s xin[1:0]/d xin[1:0] = 10 : address incremented with initialization the address is incremented by an amount equal to the specified data size when one data transfer is com - pleted. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. s xin[1:0]/d xin[1:0] = 11 : address incremented without initialization the address is incremented by an amount equal to the specified data size when one data transfer is com - pleted. the address that has been incremented during transfer does not return to the initial value. advanced mode (hsdmaadv (d 0/0x30119c) = 1) the address control conditions set using s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x ) and d xin[1:0 ] (d[13:12]/ 0 x 30112 a + 0 x 10 ? x ) are effective in advanced mode. furthermore, advanced mode allows selection of address decremented with initialization. this condition can be selected using the s x id (d4/0x301162 + 0x10? x ) and d xid (d5/0x301162 + 0x10? x ). ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) ? d x id : ch. x destination address control bit in the hsdma ch. x control register for adv mode (d5/0x301162 + 0x10? x ) when s x id (d4/0x301162 + 0x10? x ) and/or d x id (d5/0x301162 + 0x10? x ) are set to 0 (default), the condi - tions selected using s x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 301126 + 0 x 10 ? x ) and/or d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) are effective. when s x id (d4/0x301162 + 0x10? x ) and/or d x id (d5/0x301162 + 0x10? x ) are set to 1, address decremented with initialization is selected. s x id/d xid = 1 : address decremented with initialization the address is decremented by an amount equal to the specified data size when one data transfer is com - pleted. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.3.4 setting the registers in single-address mode make sure that the hsdma channel is disabled (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before setting the control information. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) address mode the address mode select bit dualm x (d15/0x301122 + 0x10? x ) should be set to 0 (single-address mode). this bit is set to 0 at initial reset. ? dualm x : ch. x address mode select bit in the hsdma ch. x control register (d15/0x301122 + 0x10? x ) transfer mode a transfer mode should be set using d xmod[1:0] (d[15:14]/0x30112a + 0x10? x). ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) table ii. 1.3.4.1 transfer mode d x mod1 1 1 0 0 d x mod0 1 0 1 0 mode in v alid bloc k transf er mode successiv e transf er mode single transf er mode refer to the explanation in section ii. 1.3.3, setting the registers in dual-address mode. direction of transfer the direction of data transfer should be set using d xdir (d14/0x301122 + 0x10? x). ? d x dir : ch. x transfer direction control bit in the hsdma ch. x control register (d14/0x301122 + 0x10? x ) memory write operations (data transfer from i/o device to memory) are specified by writing 1 and memory read operations (data transfer from memory to i/o device) are specified by writing 0. transfer data size standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) datsize x (d14/0x301126 + 0x10? x) is used to set the unit size of data to be transferred. a half-word size ( 16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, wordsize x (d0/0x301162 + 0x10? x ) is provided to select a word size (32 bits) in addi - tion to a half-word size and byte size that can be selected using datsize x (d14/0x301126 + 0x10? x). ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) table ii. 1.3.4.2 transfer data size selectable in advanced mode w ordsize x 1 0 0 t ransfer data siz e word (32 bits) half-word (16 bits) byte (8 bits) da tsize x x 1 0 datsize x (d14/0x301126 + 0x10? x ) and wordsize x (d0/0x301162 + 0x10? x ) are used to set the unit size of data to be transferred.
ii bus modules: high-speed dma (hsdma) ii-1-12 epson s1c33e08 technical manual block length when using block transfer mode (d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) = 10 ), the data block length (in units of the selected transfer data size) should be set using blklen x[7:0] (d[7:0]/0x301120 + 0x10? x). ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) in single transfer and successive transfer modes, blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ) are used as bits 7 C0 of the transfer counter. note : when performing data transfer in block transfer mode, the block size must not be set to 0. transfer counter block transfer mode in block transfer mode, up to 16 bits of transfer count can be specified using tc x_l[7:0 ] (d[15:8]/0x301120 + 0x10? x ) and tc x_h[7:0] (d[7:0]/0x301122 + 0x10? x). ? tc x _l[7:0] : ch. x transfer counter [7:0] bits in the hsdma ch. x transfer counter register (d[15:8]/0x301120 + 0x10? x ) ? tc x _h[7:0] : ch. x transfer counter [15:8] bits in the hsdma ch. x control register (d[7:0]/0x301122 + 0x10? x ) single transfer and successive transfer modes in single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using blklen x [7:0 ] (d[7:0 ]/0x301120 + 0x10? x ), tc x _l[ 7:0 ] (d[15:8 ]/0x301120 + 0x10? x ) and tc x _h[ 7:0] (d[7:0]/0x301122 + 0x10? x ). memory address standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) in standard mode, s x adrl[ 15:0 ] (d[15:0 ]/0x301124 + 0x10? x ) and s x adrh[ 11:0 ] (d[11:0 ]/0x301126 + 0x10? x) are used to specify a 28-bit memory address. ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (d[15:0]/0x301124 + 0x10? x ) ? s x adrh[11:0] : ch. x source address[27:16] in the hsdma ch. x high-order source address setup register (d[11:0]/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, s x adrl[ 15:0 ] (d[15:0 ]/0x301164 + 0x10? x ) and s x adrh[ 15:0 ] (d[15:0 ]/0x301166 + 0x10? x) are used to specify a 32-bit memory address. ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register for adv mode (d[15:0]/0x301164 + 0x10? x ) ? s x adrh[15:0] : ch. x source address[31:16] in the hsdma ch. x high-order source address setup register for adv mode (d[15:0]/0x301166 + 0x10? x ) note : in advanced mode, be sure to use the control registers for advanced mode to set a memory ad - dress. in single-address mode, data transfer is performed between the memory connected to the system interface and an external i/o device. the i/o device is accessed directly by the #dmaack x signal, so it is unnecessary to specify an address. d xadrl[15:0 ] (d[15:0]/0x301168 + 0x10? x ) and d xadrh[15:0 ] (d[11:0]/0x30116 a + 0x10? x) are not used in single-address mode. address increment/decrement control standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) the memory addresses can be incremented or decremented when one data transfer is completed. s x in[ 1:0] (d[13:12]/0x301126 + 0x10? x) is used to set this function. ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x )
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 1.3.4.3 address control s x in1 1 1 0 0 s x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed advanced mode (hsdmaadv (d 0/0x30119c) = 1) the address control condition set using s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is effective in advanced mode. furthermore, advanced mode allows selection of address decremented with initialization. this condi - tion can be selected using the s xid (d4/0x301162 + 0x10? x). ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) when s x id (d4/0x301162 + 0x10? x ) is set to 0 (default), the condition selected using s xin[1:0 ] (d[13:12]/ 0x301126 + 0x10? x ) is effective. when s x id (d4/0x301162 + 0x10? x ) is set to 1, address decremented with initialization is selected. refer to the explanation in section ii. 1.3.3, setting the registers in dual-address mode. d xin[1:0 ] (d[13:12]/0x30112 a + 0x10? x ) and d x id (d5/0x301162 + 0x10? x ) are not used in single-address mode.
ii bus modules: high-speed dma (hsdma) ii-1-14 epson s1c33e08 technical manual ii.1.4 enabling/disabling dma transfer the hsdma transfer is enabled by writing 1 to hs x_en (d0/0x30112c + 0x10? x). ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) however, the control information must always be set correctly before enabling a dma transfer. note that the control information cannot be set when hs x_en (d0/0x30112c + 0x10? x) = 1. when hs x_en (d0/0x30112c + 0x10? x) is set to 0, hsdma requests are no longer accepted. when a dma transfer is completed (transfer counter = 0 ), hs x _en (d0/0x30112 c + 0x10? x ) is reset to 0 to dis - able the following trigger inputs.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.5 trigger source a hsdma trigger source for each channel can be selected from among 15 types using hsd x s[ 3:0 ] (d[7:0 ]/ 0x300298, d[7:0]/0x300299 ). this function is supported by the interrupt controller. ? hsd0s[3:0] : ch.0 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[3:0]/0x300298) ? hsd1s[3:0] : ch.1 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[7:4]/0x300298) ? hsd2s[3:0] : ch.2 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[3:0]/0x300299) ? hsd3s[3:0] : ch.3 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[7:4]/0x300299) table ii. 1.5.1 shows the setting value and the corresponding trigger source. table ii. 1.5.1 hsdma trigger source v alue 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 ch.0 trigger sour ce softw are tr igger #dmareq0 input (f alling edge) #dmareq0 input (r ising edge) po rt 0 input po rt 4 input (reser v ed) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left ser ial i/f ch.0 rx b uff er full ser ial i/f ch.0 tx b uff er empty a/d con v ersion completion po rt 8 input (spi interr upt) po rt 12 input ch.1 trigger sour ce softw are tr igger #dmareq1 input (f alling edge) #dmareq1 input (r ising edge) po rt 1 input po rt 5 input (reser v ed) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s r ight ser ial i/f ch.1 rx b uff er full ser ial i/f ch.1 tx b uff er empty a/d con v ersion completion po rt 9 input (usb pdreq) po rt 13 input ch.2 trigger sour ce softw are tr igger #dmareq2 input (f alling edge) #dmareq2 input (r ising edge) po rt 2 input po rt 6 input (reser v ed) 16-bit timer 2 compare b 16-bit timer 2 compare a (reser v ed) spi transmit dma request ser ial i/f ch.2 rx b uff er full ser ial i/f ch.2 tx b uff er empty a/d con v ersion completion po rt 10 input (usb interr upt) po rt 14 input ch.3 trigger sour ce softw are tr igger #dmareq3 input (f alling edge) #dmareq3 input (r ising edge) po rt 3 input po rt 7 input (reser v ed) 16-bit timer 3 compare b 16-bit timer 3 compare a (reser v ed) spi receiv e dma request (reser v ed) (reser v ed) a/d con v ersion completion po rt 11 input (dcsio interr upt) po rt 15 input by selecting a cause of interrupt with the hsdma trigger set-up register, the hsdma channel is invoked when the selected cause of interrupt occurs. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. the cause of interrupt that invokes hsdma sets the cause-of-interrupt flag and hsdma does not reset the flag. consequently, when the dma trans - fer is completed (even if the transfer counter is not 0 ), an interrupt request to the cpu will be generated if the inter - rupt has been enabled. to generate an interrupt only when the transfer counter reaches 0 , disable the interrupt by the cause of interrupt that invokes hsdma and use the hsdma transfer completion interrupt. when software trigger is selected, the hsdma channel can be invoked by writing 1 to hst x (d x/0x30029a). ? hst x : ch. x software trigger bit in the hsdma software trigger register (d x /0x30029a) when the selected trigger occurs, the trigger flag is set to 1 to invoke the hsdma channel. the hsdma starts a dma transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. this makes it possible to queue the hsdma triggers that have been generated. the trigger flag can be read and cleared using hs x_tf (d0/0x30112e + 0x10? x). ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) by writing 1 to this bit, the set trigger flag can be cleared if the dma transfer has not been started. when this bit is read, 1 indicates that the flag is set and 0 indicates that the flag is cleared. note : the following shows the priority order of channels when dma triggers with the same interrupt level occur in two or more hsdma and idma channels. priority channel high lo w hsdma ch.0 > ch.1 > ch.2 > ch.3 > idma softw are tr igger > idma hardw are tr igger
ii bus modules: high-speed dma (hsdma) ii-1-16 epson s1c33e08 technical manual ii.1.6 operation of hsdma an hsdma channel starts data transfer by the selected trigger source. make sure that transfer conditions and a trigger source are set and the hsdma channel is enabled before starting a dma transfer. ii.1.6.1 operation in dual-address mode in dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the sramc and sdramc. hsdma has three transfer modes, in each of which data transfer operates differently. the following describes the operation of hsdma in each transfer mode. single transfer mode (dual-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 00 oper - ates in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after trans - ferring one data unit of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) the operation of hsdma in single transfer mode is shown by the flow chart in figure ii. 1.6.1.1. start end data read from source (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en data write to destination (1 byte, 1 half word or 1 word) transfer counter - 1 set cause-of-interrupt flag fhdm x transfer counter = 0 n y increment/decrement address ? ? : according to s x in/d x in or s x id/d x id settings figure ii.1.6.1.1 operation flow in single transfer mode
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) (2 ) the read data is written to the destination address. (3 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/ d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) or s x id (d 4 / 0 x 301162 + 0 x 10 ? x )/d x id (d 5 / 0 x 301162 + 0 x 10 ? x ) settings. ? 1 ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? d x in[1:0] : ch. x destination address control bits in the hsdma ch. x high-order destination address setup register (d[13:12]/0x30112a + 0x10? x ) ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) ? d x id : ch. x destination address control bit in the hsdma ch. x control register for adv mode (d5/0x301162 + 0x10? x ) (4 ) the transfer counter is decremented. (5 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-18 epson s1c33e08 technical manual successive transfer mode (dual-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 01 oper - ates in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of hsdma in successive transfer mode is shown by the flow chart in figure ii. 1.6.1.2. start end transfer counter - 1 transfer counter = 0 n y increments/decrements address ? ? : according to s x in/d x in or s x id/d x id settings data read from source (1 byte, 1 half word or 1 word) data write to destination (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x restores initial values to address ? ? : according to s x in/d x in or s x id/d x id settings figure ii.1.6.1.2 operation flow in successive transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. (2 ) the read data is written to the destination address. (3 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/ d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) or s x id (d 4 / 0 x 301162 + 0 x 10 ? x )/d x id (d 5 / 0 x 301162 + 0 x 10 ? x ) settings. ? 1 (4 ) the transfer counter is decremented. (5 ) steps (1) to (4) are repeated until the transfer counter reaches 0. (6 ) the address returns to the initial value if s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/d xin[1:0 ] (d[13:12]/ 0x30112a + 0x10? x) is 10 or s xid (d4/0x301162 + 0x10? x)/d xid (d5/0x301162 + 0x10? x) is 1. ? 1 (7 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block transfer mode (dual-address mode) the channel for which d x mod[ 1 : 0 ] (d[ 15 : 14 ]/ 0 x 30112 a + 0 x 10 ? x ) in control information is set to 10 operates in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of hsdma in block transfer mode is shown by the flow chart in figure ii. 1.6.1.3. ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) start end block size - 1 restores initial values to block size and address ? block size = 0 1-block transfer n y transfer counter - 1 transfer counter = 0 n y ? : according to s x in/d x in or s x id/d x id settings data read from source (1 byte, 1 half word or 1 word) data write to destination (1 byte, 1 half word or 1 word) increments/decrements address ? ? : according to s x in/d x in or s x id/d x id settings clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x figure ii.1.6.1.3 operation flow in block transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. (2 ) the read data is written to the destination address. (3) the address is incremented or decremented and blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) is decremented. (4 ) steps (1) to (3) are repeated until blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) reaches 0. (5 ) the address returns to the initial value if s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/d xin[1:0 ] (d[13:12]/ 0x30112a + 0x10? x) is 10 or s xid (d4/0x301162 + 0x10? x)/d xid (d5/0x301162 + 0x10? x) is 1. ? 1 (6 ) the transfer counter is decremented. (7 ) steps (1) to (6) are repeated until the transfer counter reaches 0. (8 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-20 epson s1c33e08 technical manual ii.1.6.2 operation in single-address mode in single-address mode, data read/write operations are performed simultaneously. the data transfer direction (read from i/o device write to memory or read from memory write to i/o device) is set using d x dir (d 14 / 0 x 301122 + 0x10? x ). ? d x dir : ch. x transfer direction control bit in the hsdma ch. x control register (d14/0x301122 + 0x10? x ) single-address mode has three transfer modes, in each of which data transfer operates differently. the following describes the operation of hsdma in single-address mode. #dmaack x signal output and bus operation when the hsdma circuit accepts the dma request, it outputs a low-level pulse from the #dmaack x pin and starts bus operation for the memory at the same time. the contents of this bus operation are as follows: ? data transfer from i/o device to memory (d xdir (d14/0x301122 + 0x10? x) = 1) the address that has been set in the memory address register is output to the address bus. a write operation is performed under the interface conditions set on the area to which the memory at the desti - nation of transfer belongs. the data bus is left floating. the external i/o device outputs the transfer data onto the data bus using the #dmaack x signal as the read sig - nal. the memory takes in this data using the write signal. ? data transfer from memory to an i/o device (d xdir (d14/0x301122 + 0x10? x) = 0 , default) the address that has been set in the memory address register is output to the address bus. a read operation is performed under the interface conditions set on the area to which the memory at the source of transfer belongs. the memory outputs the transfer data onto the data bus using the read signal. the external i/o device takes in the data from the data bus using the #dmaack x signal as the write signal. the number of bus operations for a dma transfer is decided according to the transfer data size and i/o device size as shown in the table below. table ii. 1.6.2.1 number of bus operations per dma transfer t ransfer data siz e 32 bits 32 bits 16 bits other number of b us operations 4 2 2 1 i/o de vice siz e 8 bits 16 bits 8 bits notes : ? a 0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for single-address transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. #dmaend x signal output when the transfer counter reaches 0 , the end-of-transfer signal is output from the #dmaend x pin indicating that a specified number of transfers has been completed. at the same time, the cause of interrupt (completion of hsdma) is generated.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 single transfer mode (single-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 00 oper - ates in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after trans - ferring one data unit of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) the operation of hsdma in single transfer mode is shown by the flow chart in figure ii. 1.6.2.1. start end clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en transfer counter - 1 set cause-of-interrupt flag fhdm x transfer counter = 0 n y increment/decrement address ? ? : according to s x in or s x id settings data read from source and data write to destination (1 byte, 1 half word or 1 word) figure ii.1.6.2.1 operation flow in single transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ? 1 ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) (2 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x) or s xid (d4/0x301162 + 0x10? x) settings. ? 2 ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) (3 ) the transfer counter is decremented. (4 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x )
ii bus modules: high-speed dma (hsdma) ii-1-22 epson s1c33e08 technical manual ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ? s x adrl : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (std mode: d[15:0]/0x301124 + 0x10? x , adv mode: d[15:0]/0x301164 + 0x10? x ) ? s x adrh : ch. x source address (high-order bits) in the hsdma ch. x high-order source address setup register (std mode: d[11:0]/0x301126 + 0x10? x , adv mode: d[15:0]/0x301166 + 0x10? x ) ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0. successive transfer mode (single-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 01 oper - ates in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of hsdma in successive transfer mode is shown by the flow chart in figure ii. 1.6.2.2. start end transfer counter - 1 transfer counter = 0 n y increments/decrements address ? ? : according to s x in or s x id settings data read from source and data write to destination (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x restores initial values to address ? ? : according to s x in or s x id settings figure ii.1.6.2.2 operation flow in successive transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ? 1 (2 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x) or s xid (d4/0x301162 + 0x10? x) settings. ? 2 (3 ) the transfer counter is decremented. (4 ) steps (1) to (3) are repeated until the transfer counter reaches 0. (5 ) the address returns to the initial value if s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is 10 or s x id (d 4/ 0x301162 + 0x10? x) is 1. ? 2 (6 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block transfer mode (single-address mode) the channel for which d x mod[ 1 : 0 ] (d[ 15 : 14 ]/ 0 x 30112 a + 0 x 10 ? x ) in control information is set to 10 operates in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of hsdma in block transfer mode is shown by the flow chart in figure ii. 1.6.2.3. ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) start end block size - 1 restores initial values to block size and address ? block size = 0 1-block transfer n y transfer counter - 1 transfer counter = 0 n y ? : according to s x in or s x id settings increments/decrements address ? ? : according to s x in or s x id settings clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x data read from source and data write to destination (1 byte, 1 half word or 1 word) figure ii.1.6.2.3 operation flow in block transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ?1 (2 ) the address is incremented or decremented and blklen x [ 7 : 0 ] (d[ 7 : 0 ]/ 0 x 301120 + 0 x 10 ? x ) is decremented. (3 ) steps (1) to (2) are repeated until blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) reaches 0. (4 ) the address returns to the initial value if s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is 10 or s x id (d 4/ 0x301162 + 0x10? x) is 1. ? 2 (5 ) the transfer counter is decremented. (6 ) steps (1) to (5) are repeated until the transfer counter reaches 0. (7 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-24 epson s1c33e08 technical manual ii.1.7 interrupt function of hsdma the dma controller can generate an interrupt when the transfer counter in each hsdma channel reaches 0. furthermore, channels 0 and 1 can invoke idma using their cause of interrupt. control registers of the interrupt controller table ii. 1.7.1 shows the control registers of the interrupt controller that are provided for each channel. table ii. 1.7.1 control registers of interrupt controller channel ch. 0 ch. 1 ch. 2 ch. 3 cause-of-interrupt fla g fhdm0(d0/0x300281) fhdm1(d1/0x300281) fhdm2(d2/0x300281) fhdm3(d3/0x300281) interrupt priority register phsd0l[2:0](d[2:0]/0x300263) phsd1l[2:0](d[6:4]/0x300263) phsd2l[2:0](d[2:0]/0x300264) phsd3l[2:0](d[6:4]/0x300264) interrupt enable register ehdm0(d0/0x300271) ehdm1(d1/0x300271) ehdm2(d2/0x300271) ehdm3(d3/0x300271) the hsdma controller sets the hsdma cause-of-interrupt flag to 1 when the transfer counter reaches 0 after completing a series of hsdma transfers. if the corresponding bit of the interrupt enable register is set to 1 at this time, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit set to 0 . the hsdma cause-of-interrupt flag is always set to 1 when the data transfer in each channel is com - pleted no matter what value the interrupt enable register bit is set to. (this is true even when it is set to 0.) the interrupt priority register sets an interrupt priority level ( 0 to 7 ). an interrupt request to the cpu is accepted only when there is no other interrupt request of higher priority. furthermore, it is only when the psr's ie bit = 1 (interrupt enable) and the set value of il is smaller than the hsdma interrupt level which is set in the inter - rupt priority register that the cpu actually accepts a hsdma interrupt. for details about the interrupt control register and for the device operation when an interrupt occurs, refer to section iii. 2 , interrupt controller (itc). intelligent dma intelligent dma (idma) can be invoked by the end-of-transfer interrupt source of channels 0 and 1 of hs - dma. the following shows the idma channels set in hsdma: idma channel channel 0 end-of-transfer interrupt: 0x05 channel 1 end-of-transfer interrupt: 0x06 before idma can be invoked, the corresponding bits of the idma request and idma enable registers must be set to 1. settings of transfer conditions on the idma side are also required. table ii. 1.7.2 control bits for idma transfer channel ch. 0 ch. 1 idma request bit rhdm0(d4/0x300290) rhdm1(d5/0x300290) idma enable bit dehdm0(d4/0x300294) dehdm1(d5/0x300294) if the idma request and enable bits are set to 1 , idma is invoked through generation of a cause of interrupt. no interrupt request is generated at that point. an interrupt request is generated after the dma transfer is com - pleted. the registers can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on idma transfers and interrupt control upon completion of idma transfer, refer to section ii. 2, intelligent dma (idma). trap vector the trap vector addresses for causes of interrupt in each channel are set by default as follows: channel 0 end-of-transfer interrupt: 0xc00058 channel 1 end-of-transfer interrupt: 0xc0005c channel 2 end-of-transfer interrupt: 0xc00060 channel 3 end-of-transfer interrupt: 0xc00064 note that the trap table base address can be modified using the ttbr register.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.8 hsdma operating clock the hsdma circuit is clocked by the dma_clk clock (= mclk) generated by the cmu. for details on how to control the clock, see section iii. 1, clock management unit (cmu). controlling the supply of the hsdma operating clock dma_clk is supplied to the dma controller with default settings. when dma transfer is not performed, the clock supply can be turned off using dma_cke (d 1/0x301b04 ) to reduce the amount of power consumed on the chip. ? dma_cke : dmac clock control bit in the gated clock control register 1 (d1/0x301b04) setting dma_cke (d 1/0x301b04 ) to 0 (initially 1 ) turns off the corresponding clock supply to the dma con - troller. clock state in standby mode the supply of dma_clk stops depending on type of standby mode. halt mode: dma_clk is supplied the same way as in normal mode (when dma_cke = 1). sleep mode: the supply of dma_clk stops. therefore, the dma controller also stops operating in sleep m ode.
ii bus modules: high-speed dma (hsdma) ii-1-26 epson s1c33e08 technical manual ii.1.9 details of control registers table ii. 1.9.1 list of hsdma registers address 0x00301120 0x00301122 0x00301124 0x00301126 0x00301128 0x0030112a 0x0030112c 0x0030112e 0x00301130 0x00301132 0x00301134 0x00301136 0x00301138 0x0030113a 0x0030113c 0x0030113e 0x00301140 0x00301142 0x00301144 0x00301146 0x00301148 0x0030114a 0x0030114c 0x0030114e 0x00301150 0x00301152 0x00301154 0x00301156 0x00301158 0x0030115a 0x0030115c 0x0030115e function sets ch.0 low-order transfer counter data and block length. sets ch.0 address mode and high-order transfer counter data. sets ch.0 low-order source address. sets ch.0 high-order source address, transfer data size, and source address inc/dec condition. sets ch.0 low-order destination address. sets ch.0 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.0 dma transfer. ch.0 trigger status sets ch.1 low-order transfer counter data and block length. sets ch.1 address mode and high-order transfer counter data. sets ch.1 low-order source address. sets ch.1 high-order source address, transfer data size, and source address inc/dec condition. sets ch.1 low-order destination address. sets ch.1 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.1 dma transfer. ch.1 trigger status sets ch.2 low-order transfer counter data and block length. sets ch.2 address mode and high-order transfer counter data. sets ch.2 low-order source address. sets ch.2 high-order source address, transfer data size, and source address inc/dec condition. sets ch.2 low-order destination address. sets ch.2 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.2 dma transfer. ch.2 trigger status sets ch.3 low-order transfer counter data and block length. sets ch.3 address mode and high-order transfer counter data. sets ch.3 low-order source address. sets ch.3 high-order source address, transfer data size, and source address inc/dec condition. sets ch.3 low-order destination address. sets ch.3 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.3 dma transfer. ch.3 trigger status register name hsdma ch.0 transfer counter register (phs0_cnt) hsdma ch.0 control register hsdma ch.0 low-order source address setup register (phs0_sadr) hsdma ch.0 high-order source address setup register hsdma ch.0 low-order destination address setup register (phs0_dadr) hsdma ch.0 high-order destination address setup register hsdma ch.0 enable register (phs0_en) hsdma ch.0 trigger flag register (phs0_tf) hsdma ch.1 transfer counter register (phs1_cnt) hsdma ch.1 control register hsdma ch.1 low-order source address setup register (phs1_sadr) hsdma ch.1 high-order source address setup register hsdma ch.1 low-order destination address setup register (phs1_dadr) hsdma ch.1 high-order destination address setup register hsdma ch.1 enable register (phs1_en) hsdma ch.1 trigger flag register (phs1_tf) hsdma ch.2 transfer counter register (phs2_cnt) hsdma ch.2 control register hsdma ch.2 low-order source address setup register (phs2_sadr) hsdma ch.2 high-order source address setup register hsdma ch.2 low-order destination address setup register (phs2_dadr) hsdma ch.2 high-order destination address setup register hsdma ch.2 enable register (phs2_en) hsdma ch.2 trigger flag register (phs2_tf) hsdma ch.3 transfer counter register (phs3_cnt) hsdma ch.3 control register hsdma ch.3 low-order source address setup register (phs3_sadr) hsdma ch.3 high-order source address setup register hsdma ch.3 low-order destination address setup register (phs3_dadr) hsdma ch.3 high-order destination address setup register hsdma ch.3 enable register (phs3_en) hsdma ch.3 trigger flag register (phs3_tf) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 address 0x00301162 0x00301164 0x00301166 0x00301168 0x0030116a 0x00301172 0x00301174 0x00301176 0x00301178 0x0030117a 0x00301182 0x00301184 0x00301186 0x00301188 0x0030118a 0x00301192 0x00301194 0x00301196 0x00301198 0x0030119a 0x0030119c 0x0030119e function selects ch.0 adv mode functions. sets ch.0 low-order source address for adv mode. sets ch.0 high-order source address for adv mode. sets ch.0 low-order destination address for adv mode. sets ch.0 high-order destination address for adv mode. selects ch.1 adv mode functions. sets ch.1 low-order source address for adv mode. sets ch.1 high-order source address for adv mode. sets ch.1 low-order destination address for adv mode. sets ch.1 high-order destination address for adv mode. selects ch.2 adv mode functions. sets ch.2 low-order source address for adv mode. sets ch.2 high-order source address for adv mode. sets ch.2 low-order destination address for adv mode. sets ch.2 high-order destination address for adv mode. selects ch.3 adv mode functions. sets ch.3 low-order source address for adv mode. sets ch.3 high-order source address for adv mode. sets ch.3 low-order destination address for adv mode. sets ch.3 high-order destination address for adv mode. selects standard or advanced mode. sets sequential access time for idma and hsdma. register name hsdma ch.0 control register (phs0_advmode) for adv mode hsdma ch.0 low-order source address setup register (phs0_ad_sadr) for adv mode hsdma ch.0 high-order source address setup register for adv mode hsdma ch.0 low-order destination address setup register (phs0_adv_dadr) for adv mode hsdma ch.0 high-order destination address setup register for adv mode hsdma ch.1 control register (phs1_advmode) for adv mode hsdma ch.1 low-order source address setup register (phs1_ad_sadr) for adv mode hsdma ch.1 high-order source address setup register for adv mode hsdma ch.1 low-order destination address setup register (phs1_adv_dadr) for adv mode hsdma ch.1 high-order destination address setup register for adv mode hsdma ch.2 control register (phs2_advmode) for adv mode hsdma ch.2 low-order source address setup register (phs2_ad_sadr) for adv mode hsdma ch.2 high-order source address setup register for adv mode hsdma ch.2 low-order destination address setup register (phs2_adv_dadr) for adv mode hsdma ch.2 high-order destination address setup register for adv mode hsdma ch.3 control register (phs3_advmode) for adv mode hsdma ch.3 low-order source address setup register (phs3_ad_sadr) for adv mode hsdma ch.3 high-order source address setup register for adv mode hsdma ch.3 low-order destination address setup register (phs3_adv_dadr) for adv mode hsdma ch.3 high-order destination address setup register for adv mode hsdma std/adv mode select register (phs_cntlmode) dma sequential access time register (phs_acctime) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 the following describes each hsdma control register. the hsdma control registers are mapped in the 16 -bit device area from 0x301120 to 0x30119 e, and can be ac - cessed in units of half-words or bytes. note : when setting the hsdma control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: high-speed dma (hsdma) ii-1-28 epson s1c33e08 technical manual 0x301120C0x301150: hsdma ch. x transfer counter registers (phs x _cnt) name address register name bit function setting init. r/w remarks tc x _l7 tc x _l6 tc x _l5 tc x _l4 tc x _l3 tc x _l2 tc x _l1 tc x _l0 blklen x 7 blklen x 6 blklen x 5 blklen x 4 blklen x 3 blklen x 2 blklen x 1 blklen x 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x transfer c ounter[7:0 ] (block transfer mode) ch. x transfer counter[15:8] (single/successive transfer mode) ch. x block lengt h (block transfer mode) ch. x transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301120 | 00301150 (hw) hsdma ch. x transfer counter register (phs x _cnt) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301120 hsdma ch.0 transfer counter register (phs0_cnt) 0x301130 hsdma ch.1 transfer counter register (phs1_cnt) 0x301140 hsdma ch.2 transfer counter register (phs2_cnt) 0x301150 hsdma ch.3 transfer counter register (phs3_cnt) d[15:8] tc x _l[7:0]: ch. x transfer counter bits set the data transfer count. (default: 0x00) in block transfer mode, tc x_l[7:0 ] is bits[7:0 ] of the transfer counter. in single or successive transfer mode, tc x_l[7:0] is bits[15:8 ] of the transfer counter. this counter is decremented each time a dma transfer in the corresponding channel is performed. when the counter reaches 0 , a cause of interrupt is generated. in single-address mode, the end-of-trans - fer signal is output from the #dmaend x pin at the same time. even when the counter is 0 , a dma request is accepted and the counter is decremented to 0xffff (or 0xffffff). be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing and reading to and from the counter. d[7:0] blklen x [7:0]: ch. x block length bits in block transfer mode, these bits are used to specify a transf er block size. (default: 0x00) a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0]. in single or successive transfer mode, these bits are used to specify the 8 low-order bits of the transfer counter. note : when performing data transfer in block transfer mode, the block size must not be set to 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301122C0x301152: hsdma ch. x control registers name address register name bit function setting init. r/w remarks C C dualm x d x dir C tc x _h7 tc x _h6 tc x _h5 tc x _h4 tc x _h3 tc x _h2 tc x _h1 tc x _h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x address mode selection d) invalid s) ch. x transfer direction control reserved ch. x transfer counter[15:8] (block transfer mode) ch. x transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301122 | 00301152 (hw) hsdma ch. x control register note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301122 hsdma ch.0 control register 0x301132 hsdma ch.1 control register 0x301142 hsdma ch.2 control register 0x301152 hsdma ch.3 control register d15 dualm x : ch. x address mode select bit select an address mode. 1 (r/w): dual-address mode 0 (r/w): single-address mode (default) when 1 is written to dualm x , the hsdma channel enters dual-address mode that allows specifica - tion of source and destination addresses. when 0 is written, the hsdma channel enters single-address mode for high-speed data transfer between the external memory and an i/o device. d14 d x dir: ch. x transfer direction control bit control the direction of data transfer in single-address mode. 1 (r/w): memory write 0 (r/w): memory read (default) data transfer from an external i/o device to external memory (or an external/internal i/o) is performed by writing 1 to d x dir. data transfer from external memory (or an external/internal i/o) to an external i/o is performed by writing 0. this bit is effective only in single-address mode. d[13:8] reserved d[7:0] tc x _h[7:0]: ch. x transfer counter bits set the data transfer count. (default: 0x00) in block transfer mode, tc x_h[7:0 ] is bits[15:8 ] of the transfer counter. in single or successive transfer mode, tc x_h[7:0] is bits[23:16 ] of the transfer counter. this counter is decremented each time a dma transfer in the corresponding channel is performed. when the counter reaches 0 , a cause of interrupt is generated. in single-address mode, the end-of-trans - fer signal is output from the #dmaend x pin at the same time. even when the counter is 0 , a dma request is accepted and the counter is decremented to 0xffff (or 0xffffff). be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing and reading to and from the counter.
ii bus modules: high-speed dma (hsdma) ii-1-30 epson s1c33e08 technical manual 0x301124C0x301154: hsdma ch. x low-order source address setup registers (phs x _sadr) name address register name bit function setting init. r/w remarks s x adrl15 s x adrl14 s x adrl13 s x adrl12 s x adrl11 s x adrl10 s x adrl9 s x adrl8 s x adrl7 s x adrl6 s x adrl5 s x adrl4 s x adrl3 s x adrl2 s x adrl1 s x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[15:0] s) ch. x memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301124 | 00301154 (hw) hsdma ch. x low-order source address setup register (phs x _sadr) note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301124 hsdma ch.0 low-order source address setup register (phs0_sadr) 0x301134 hsdma ch.1 low-order source address setup register (phs1_sadr) 0x301144 hsdma ch.2 low-order source address setup register (phs2_sadr) 0x301154 hsdma ch.3 low-order source address setup register (phs3_sadr) d[15:0] s x adrl[15:0]: ch. x source address[15:0] (for standard mode) in dual-address mode, these bits are used to specify a source address. in single-address mode, an exter - nal memory address at the destination or source of transfer is specified. use s xadrl[15:0] to set the 16 low-order bits of the address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) or s x id (d4/0x301162 + 0x10? x )) according to the transfer data size each time a dma transfer in the cor - responding channel is performed. notes : ? the following areas cannot be used for dma transfer: dual-address mode: area 0, area 2 single-address mode: area 0, area 1, area 2, area 3, area 6 ? single-address mode does not allow data transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? use s x adrl[15:0] (d[15:0]/0x301164 + 0x10? x ) and s x adrh[15:0] (d[15:0]/0x301166 + 0x10? x ) for specifying an address in advanced mode.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301126C0x301156: hsdma ch. x high-order source address setup registers name address register name bit function setting init. r/w remarks C datsize x s x in1 s x in0 s x adrh11 s x adrh10 s x adrh9 s x adrh8 s x adrh7 s x adrh6 s x adrh5 s x adrh4 s x adrh3 s x adrh2 s x adrh1 s x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch. x transfer data size d) ch. x source address control s) ch. x memory address control d) ch. x source address[27:16] s) ch. x memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301126 | 00301156 (hw) 1 half word 0 byte hsdma ch. x high-order source address setup register note: d) dual address mode s) single address mode 11 10 01 00 s xin[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed C note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301126 hsdma ch.0 high-order source address setup register 0x301136 hsdma ch.1 high-order source address setup register 0x301146 hsdma ch.2 high-order source address setup register 0x301156 hsdma ch.3 high-order source address setup register d15 reserved d14 datsize x : ch. x transfer data size select bit select the data size to be transferred. 1 (r/w): half-word 0 (r/w): byte (default) the transfer data size is set to 16 bits by writing 1 to datsize x and set to 8 bits by writing 0. note : in advanced mode, this bit is effective when wordsize x (d0/0x301162 + 0x10? x ) = 0. the setting of this bit is ignored when wordsize x (d0/0x301162 + 0x10? x ) = 1 and the transfer data size is set to 32 bits. in standard mode, this bit is always effective regardless of the wordsize x (d0/0x301162 + 0x10? x ) setting. d[13:12] s x in[1:0]: ch. x source address control bits control the incrementing or decrementing of the memory address . table ii. 1.9.2 address control s x in1 1 1 0 0 s x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed (default: 0b00) in dual-address mode, this setting applies to the source address. in single-address mode, this setting ap - plies to the external memory address. when fixed (00 ) is selected, the source address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read from the same address. when increment without initialization (11 ) is selected, the source address is incremented by an amount equal to the data size set by datsize x (d14 ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed.
ii bus modules: high-speed dma (hsdma) ii-1-32 epson s1c33e08 technical manual when decrement without initialization (01 ) is selected, the source address is decremented in the same way. when increment with initialization (10 ) is selected, the source address is incremented by an amount equal to the data size set by datsize x (d14 ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incre - mented address returns to the initial value when the block transfer is completed. note : in advanced mode, these bits are effective when s x id (d4/0x301162 + 0x10? x ) = 0. the set - ting of these bits is ignored when s x id (d4/0x301162 + 0x10? x ) = 1 and decrement with ini - tialization is selected. in standard mode, this bit is always effective regardless of the s x id (d4/0x301162 + 0x10? x ) setting. d[11:0] s x adrh[11:0]: ch. x source address[27:16] (for standard mode) in dual-address mode, these bits are used to specify 12 high-order bits of source address. in single- address mode, 12 high-order bits of external memory address at the destination or source of transfer is specified. see s xadrl[15:0] (d[15:0]/0x301124 + 0x10? x) for more information.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301128C0x301158: hsdma ch. x low-order destination address setup registers (phs x _dadr) name address register name bit function setting init. r/w remarks d x adrl15 d x adrl14 d x adrl13 d x adrl12 d x adrl11 d x adrl10 d x adrl9 d x adrl8 d x adrl7 d x adrl6 d x adrl5 d x adrl4 d x adrl3 d x adrl2 d x adrl1 d x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301128 | 00301158 (hw) hsdma ch. x low-order destination address setup register (phs x _dadr) note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301128 hsdma ch.0 low-order destination address setup register (phs0_dadr) 0x301138 hsdma ch.1 low-order destination address setup register (phs1_dadr) 0x301148 hsdma ch.2 low-order destination address setup register (phs2_dadr) 0x301158 hsdma ch.3 low-order destination address setup register (phs3_dadr) d[15:0] d x adrl[15:0]: ch. x destination address[15:0] (for standard mode) in dual-address mode, these bits are used to specify a destinat ion address. use d xadrl[15:0] to set the 16 low-order bits of the address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by d x in[ 1:0 ] (d[13:12 ]/0x30112 a + 0x10? x ) or d xid (d5/0x301162 + 0x10? x)) according to the transfer data size each time a dma transfer in the cor - responding channel is performed. notes : ? in single-address mode, these bits are not used. ? the following areas cannot be specified for destination addresses: area 0 (a0ram), area 2 ? use d x adrl[15:0] (d[15:0]/0x301168 + 0x10? x ) and d x adrh[15:0] (d[15:0]/0x30116a + 0x10? x ) for specifying an address in advanced mode.
ii bus modules: high-speed dma (hsdma) ii-1-34 epson s1c33e08 technical manual 0x30112aC0x30115a: hsdma ch. x high-order destination address setup registers name address register name bit function setting init. r/w remarks d x mod1 d x mod0 d x in1 d x in0 d x adrh11 d x adrh10 d x adrh9 d x adrh8 d x adrh7 d x adrh6 d x adrh5 d x adrh4 d x adrh3 d x adrh2 d x adrh1 d x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x transfer mode d) ch. x destination address control s) invalid d) ch. x destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030112a | 0030115a (hw) hsdma ch. x high-order destination address setup register note: d) dual address mode s) single address mode d xmod[1:0] mode invalid block successive single d xin[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112a hsdma ch.0 high-order destination address setup register 0x30113a hsdma ch.1 high-order destination address setup register 0x30114a hsdma ch.2 high-order destination address setup register 0x30115a hsdma ch.3 high-order destination address setup register d[15:14] d x mod[1:0]: ch. x transfer mode select bits select a transfer mode. table ii. 1.9.3 transfer mode d x mod1 1 1 0 0 d x mod0 1 0 1 0 mode in v alid bloc k transf er mode successiv e transf er mode single transf er mode (default: 0b00) in single transfer mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). in successive transfer mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. in block transfer mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). d[13:12] d x in[1:0]: ch. x destination address control bits control the incrementing or decrementing of the memory address . table ii. 1.9.4 address control d x in1 1 1 0 0 d x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed (default: 0b00) in dual-address mode, this setting applies to the destination a ddress. when fixed (00 ) is selected, the destination address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always written to the same address.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 when increment without initialization (11 ) is selected, the destination address is incremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/ 0x301162 + 0x10? x) when one data transfer is completed. when decrement without initialization (01 ) is selected, the destination address is decremented in the same way. when increment with initialization (10 ) is selected, the destination address is incremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/ 0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incremented address returns to the initial value when the block transfer is com - pleted. in single-address mode, these bits are not used. note : in advanced mode, these bits are effective when d x id (d5/0x301162 + 0x10? x ) = 0. the set - ting of these bits is ignored when d x id (d5/0x301162 + 0x10? x ) = 1 and decrement with ini - tialization is selected. in standard mode, this bit is always effective regardless of the d x id (d5/0x301162 + 0x10? x ) setting. d[11:0] d x adrh[11:0]: ch. x destination address[27:16] (for standard mode) in dual-address mode, these bits are used to specify 12 high-order bits of destination address. see d xadrl[15:0] (d[15:0]/0x301128 + 0x10? x) for more information. in single-address mode, these bits are not used.
ii bus modules: high-speed dma (hsdma) ii-1-36 epson s1c33e08 technical manual 0x30112cC0x30115c: hsdma ch. x enable registers (phs x _en) name address register name bit function setting init. r/w remarks C C hs x _en d15C1 d0 reserved ch. x enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030112c | 0030115c (hw) hsdma ch. x enable register (phs x _en) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112c hsdma ch.0 enable register (phs0_en) 0x30113c hsdma ch.1 enable register (phs1_en) 0x30114c hsdma ch.2 enable register (phs2_en) 0x30115c hsdma ch.3 enable register (phs3_en) d[15:1] reserved d0 hs x _en: ch. x enable bit enable a dma transfer. 1 (r/w): enable 0 (r/w): disable (default) dma transfer is enabled by writing 1 to this bit. hsdma is placed in a state ready to accept a dma request from the #dmareq x pin or by the se - lected trigger source. dma transfer is disabled by writing 0 to this bit. when dma transfers are completed (transfer counter = 0), hs x _en is cleared by the hardware. be sure to disable dma transfers (hs x_en = 0) before setting the transfer condition.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30112eC0x30115e: hsdma ch. x trigger flag registers (phs x _tf) name address register name bit function setting init. r/w remarks C C hs x _tf d15C1 d0 reserved ch. x trigger flag clear (writing) ch. x trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030112e | 0030115e (hw) hsdma ch. x trigger flag register (phs x _tf) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112e hsdma ch.0 trigger flag register (phs0_tf) 0x30113e hsdma ch.1 trigger flag register (phs1_tf) 0x30114e hsdma ch.2 trigger flag register (phs2_tf) 0x30115e hsdma ch.3 trigger flag register (phs3_tf) d[15:1] reserved d0 hs x _tf: ch. x trigger flag clear/status bit these bits are used to check and clear the trigger flag status . 1 (r): trigger flag has been set 0 (r): trigger flag has been cleared (default) 1 (w): clear trigger flag 0 (w): has no effect the trigger flag is set when a trigger is input to the hsdma channel and is cleared when the hsdma channel starts a data transfer. by reading hs x _tf, the flag status can be checked. writing 1 to hs x_tf clears the trigger flag if the dma transfer has not been started.
ii bus modules: high-speed dma (hsdma) ii-1-38 epson s1c33e08 technical manual 0x301162C0x301192: hsdma ch. x control registers (phs x _advmode) for adv mode name address register name bit function setting init. r/w remarks C C C d x id s x id C wordsize x d15C6 d5 d4 d3C1 d0 reserved d) ch. x destination address control s) invalid d) ch. x source address control s) ch. x memory address control reserved ch. x transfer data size 1 decrement (with init.) 0 d xin[1:0] setting 1 decrement (with init.) 0 s xin[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301162 | 00301192 (hw) hsdma ch. x control register (phs x _advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize x setting notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301162 hsdma ch.0 control register (phs0 _advmode) 0x301172 hsdma ch.1 control register (phs1 _advmode) 0x301182 hsdma ch.2 control register (phs2 _advmode) 0x301192 hsdma ch.3 control register (phs3 _advmode) d[15:6] reserved d5 d x id: ch. x destination address control bit enable the address decrement function with initialization for destination address. 1 (r/w): decrement with initialization 0 (r/w): d xin[1:0 ] setting is effective (default) when this bit is set to 1 in dual-address mode, the destination address decrement function with initial - ization is enabled. the destination address is decremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ) when one data trans - fer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the ini - tial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. when this bit is set to 0, the condition set by d xin[1:0] (d[13:12]/0x30112a + 0x10? x ) is effective. in single-address mode, this bit is not used. d4 s x id: ch. x source address control bit enable the address decrement function with initialization for s ource address. 1 (r/w): decrement with initialization 0 (r/w): s xin[1:0 ] setting (default) in dual-address mode, this setting applies to the source address. in single-address mode, this setting ap - plies to the external memory address. when this bit is set to 1 , the address decrement function with initialization is enabled. the source/exter - nal memory address is decremented by an amount equal to the data size set by datsize x (d 14 / 0 x 301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. when this bit is set to 0, the condition set by s xin[1:0] (d[13:12]/0x301126 + 0x10? x ) is effective. d[3:1] reserved
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d0 wordsize x : ch. x transfer data size select bit select the data size to be transferred. 1 (r/w): word 0 (r/w): datsize x setting is effective (default) the transfer data size is set to 32 bits by writing 1 to this bit. when this bit is set to 0 , the size set by datsize x (d14/0x301126 + 0x10? x ) is effective.
ii bus modules: high-speed dma (hsdma) ii-1-40 epson s1c33e08 technical manual 0x301164C0x301196: hsdma ch. x source address setup registers (phs x _ad_sadr) for adv mode name address register name bit function setting init. r/w remarks s x adrl15 s x adrl14 s x adrl13 s x adrl12 s x adrl11 s x adrl10 s x adrl9 s x adrl8 s x adrl7 s x adrl6 s x adrl5 s x adrl4 s x adrl3 s x adrl2 s x adrl1 s x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[15:0] s) ch. x memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301164 | 00301194 (hw) hsdma ch. x low-order source address setup register (phs x _ad_sadr) for adv mode note: d) dual address mode s) single address mode s x adrh15 s x adrh14 s x adrh13 s x adrh12 s x adrh11 s x adrh10 s x adrh9 s x adrh8 s x adrh7 s x adrh6 s x adrh5 s x adrh4 s x adrh3 s x adrh2 s x adrh1 s x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[31:16] s) ch. x memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301166 | 00301196 (hw) hsdma ch. x high-order source address setup register for adv mode note: d) dual address mode s) single address mode notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301164 hsdma ch.0 low-order source address setup register (phs0_ad_sadr) 0x301166 hsdma ch.0 high-order source address setup register for adv mode 0x301174 hsdma ch.1 low-order source address setup register (phs1_ad_sadr) 0x301176 hsdma ch.1 high-order source address setup register for adv mode 0x301184 hsdma ch.2 low-order source address setup register (phs2_ad_sadr) 0x301186 hsdma ch.2 high-order source address setup register for adv mode 0x301194 hsdma ch.3 low-order source address setup register (phs3_ad_sadr) 0x301196 hsdma ch.3 high-order source address setup register for adv mode d[15:0]/0x301164C0x301194 s x adrl[15:0]: ch. x low-order source address[15:0] d[15:0]/0x301166C0x301196 s x adrh[15:0]: ch. x high-order source address[31:16] in dual-address mode, these bits are used to specify a 32 -bit source address. in single-address mode, a 32 -bit external memory address at the destination or source of transfer is specified. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) or s x id (d4/0x301162 + 0x10? x )) according to the transfer data size each time a dma transfer in the cor - responding channel is performed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 notes : ? the following areas cannot be used for dma transfer: dual-address mode: area 0, area 2 single-address mode: area 0, area 1, area 2, area 3, area 6 ? single-address mode does not allow data transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? use s x adrl[15:0] (d[15:0]/0x301124 + 0x10? x ) and s x adrh[11:0] (d[11:0]/0x301126 + 0x10? x ) for specifying an address in standard mode.
ii bus modules: high-speed dma (hsdma) ii-1-42 epson s1c33e08 technical manual 0x301168C0x30119a: hsdma ch. x destination address setup registers (phs x _adv_dadr) for adv mode name address register name bit function setting init. r/w remarks d x adrl15 d x adrl14 d x adrl13 d x adrl12 d x adrl11 d x adrl10 d x adrl9 d x adrl8 d x adrl7 d x adrl6 d x adrl5 d x adrl4 d x adrl3 d x adrl2 d x adrl1 d x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301168 | 00301198 (hw) hsdma ch. x low-order destination address setup register (phs x _adv_dadr) for adv mode note: d) dual address mode s) single address mode d x adrh15 d x adrh14 d x adrh13 d x adrh12 d x adrh11 d x adrh10 d x adrh9 d x adrh8 d x adrh7 d x adrh6 d x adrh5 d x adrh4 d x adrh3 d x adrh2 d x adrh1 d x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030116a | 0030119a (hw) hsdma ch. x high-order destination address setup register for adv mode note: d) dual address mode s) single address mode notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301168 hsdma ch. 0 low-order destination address setup register (phs 0 _adv_dadr) 0x30116 a hsdma ch.0 high-order destination address setup register for adv mode 0x301178 hsdma ch. 1 low-order destination address setup register (phs 1 _adv_dadr) 0x30117 a hsdma ch.1 high-order destination address setup register for adv mode 0x301188 hsdma ch. 2 low-order destination address setup register (phs 2 _adv_dadr) 0x30118 a hsdma ch.2 high-order destination address setup register for adv mode 0x301198 hsdma ch. 3 low-order destination address setup register (phs 3 _adv_dadr) 0x30119 a hsdma ch.3 high-order destination address setup register for adv mode d[15:0]/0x301168C0x301198 d x adrl[15:0]: ch. x destination address[15:0] d[15:0]/0x30116aC0x30119a d x adrh[15:0]: ch. x destination address[31:16] in dual-address mode, these bits are used to specify a 32-bit destination address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by d x in[ 1:0 ] (d[13:12 ]/0x30112 a + 0x10? x ) or d xid (d5/0x301162 + 0x10? x)) according to the transfer data size each time a dma transfer in the cor - responding channel is performed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 notes : ? in single-address mode, these bits are not used. ? the following areas cannot be specified for destination addresses: area 0 (a0ram), area 2 ? use d x adrl[15:0] (d[15:0]/0x301128 + 0x10? x ) and d x adrh[11:0] (d[11:0]/0x30112a + 0x10? x ) for specifying an address in standard mode.
ii bus modules: high-speed dma (hsdma) ii-1-44 epson s1c33e08 technical manual 0x30119c: hsdma std/adv mode select register (phs_cntlmode) name address register name bit function setting init. r/w remarks C hsdmaadv d15C1 d0 reserved standard mode/advanced mode select C 0 C r/w 0 when being read. 0030119c (hw) hsdma std/adv mode select register (phs_cntlmode) C 1 advanced mode 0 standar d mode d[15:1] reserved d0 hsdmaadv: standard/advanced mode select bit select standard or advanced mode. 1 (r/w): advanced mode 0 (r/w): standard mode (default) the hsdma in the s 1c33e08 is extended from that of the c33 std models. the s1c33e08 hsdma has two operating modes, standard (std) mode of which functions are compatible with the existing c33 std models and an advanced (adv) mode allowing use of the extended functions. table ii.1.9.5 shows differences between standard mode and advanced mode. table ii. 1.9.5 differences between standard mode and advanced mode function source/destination address bit width w ord (32-bit) data transf er address decrement function with initialization ad v anced mode 32 bits available available standar d mode 28 bits unavailable unavailable to configure the hsdma in advanced mode, set this bit to 1 . the control registers (0x301162C 0x30119 a) for the extended functions are enabled to write after this setting. notes : ? be sure to use the control registers for advanced mode when the hsdma is set to ad - vanced mode. ? standard or advanced mode currently set is applied to all the hsdma channels. it cannot be selected for each channel individually.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30119e: dma sequential access time register (phs_acctime) name address register name bit function setting init. r/w remarks C dmaacctime3 dmaacctime2 dmaacctime1 dmaacctime0 d15C4 d3 d2 d1 d0 reserved idma and hsdma sequential access time setup C 0 0 0 0 C r/w 0 when being read. 0030119e (hw) dma sequential access time register (phs_acctime) C 0 1 2 3 4 5 6 7 unlimited 64 cycles 128 cycles 192 cycles 256 cycles 320 cycles 384 cycles 448 cycles 8 9 a b c d e f 512 cycles 576 cycles 640 cycles 704 cycles 768 cycles 832 cycles 896 cycles 960 cycles d[15:4] reserved d[3:0] dmaacctime: idma and hsdma sequential access time setup bits sets the sequential access time for idma and hsdma. table ii. 1.9.6 setting the sequential access time dmaa cctime3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 dma sequential access time 960 cycles 896 cycles 832 cycles 768 cycles 704 cycles 640 cycles 576 cycles 512 cycles 448 cycles 384 cycles 320 cycles 256 cycles 192 cycles 128 cycles 64 cycles unlimited dmaa cctime2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 dmaa cctime1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 dmaa cctime0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = unlimited) when unlimited is selected, the ahb bus will not be released until a dma transfer has been com - pleted after it starts. specifying a number of cycles allows a dma transfer to be temporarily suspended when the specified cycles of data transfer have been executed to release the bus. the cpu or lcdc can perform a bus access during the suspended status. after that, the dmac resumes the data transfer that was being suspended.
ii bus modules: high-speed dma (hsdma) ii-1-46 epson s1c33e08 technical manual ii.1.10 precautions ? when setting the transfer conditions, always make sure the dma controller is inactive (hs x _en (d0/0x30112c + 0x10? x) = 0). ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) ? after an initial reset, the cause-of-interrupt flag (fhdm x (d x /0x300281 )) becomes indeterminate. always be sure to reset the flag to prevent interrupts or idma requests from being generated inadvertently. ? fhdm x : hsdma ch. x cause-of-interrupt flag in the dma interrupt cause flag register (d x /0x300281) ? to prevent an interrupt from being generated repeatedly for the same source, be sure to reset the cause-of-inter - rupt flag before setting up the psr again or executing the reti instruction. ? hsdma is given higher priority over idma (intelligent dma) and the cpu. however, since hsdma and idma share the same circuit, hsdma cannot gain the bus ownership while an idma transfer is under way. requests for hsdma invocation that have occurred during an idma transfer are kept pending until the idma transfer is completed. a request for idma invocation or an interrupt request that has occurred during a hsdma transfer are accepted after completion of the hsdma transfer. ? in dual-address mode, a0 ram (area 0 ), specific rom (area 1 ), and ivram (area 0 ) cannot be specified as the source or destination for dma transfer. while ivram (area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) can be used for dual-address transfer. ? in single-address mode, a0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for dma transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? be sure to disable the hsdma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the hsdma is enabled.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2 intelligent dma (idma) ii.2.1 functional outline of idma the s 1c33e08 contains an intelligent dma (idma), a function that allows control information to be programmed in ram. up to 128 channels can be programmed, including 41 channels that are invoked by a cause of interrupt that occurs in some internal peripheral circuit. although an additional overhead for loading and storing control information in ram may be incurred, this intelligent dma supports such functions as successive transfers, block transfers, and linking to another idma. idma is invoked by a cause of interrupt that occurs in some internal peripheral circuit or a software trigger, thereby performing a data transfer according to the control information in ram. when the transfer is completed, idma can generate an interrupt or invoke another idma according to link settings. intelligent dma transfer memory, i/o (1) the control information stored in the memory is loaded into the idma temporary register. (2) transfer data is read from the source memory or i/o device. (3) transfer data is written to the destination memory or i/o device. (4) the updated control information in the idma temporary register is written back to the memory. (3) destination memory, i/o (2) (4) (1) source dst ram or external ram control information control information transfer data transfer idma itc dma request #dmareq x sramc load/store load/store (software trigger) address bus cpu_ahb bus dma control information data bus dma data transfer request signal dma data transfer acknowledge signal dma control information transfer request signal dma control information transfer acknowledge signal hardware trigger idma ch. number data bus figure ii.2.1.1 data and control information flow in intelligent dma transfer the features of idma are outlined below. ? controller equivalent to the hsdma dual-address transfer controller ? number of channels 128 channels ? control information programmable in the ram the information table can be stored in dst ram (area 3 ) or in the external ram. (a0ram cannot be used.) ? source external memory and internal memory except areas 0 and 1 ? destination external memory and internal memory except areas 0 and 1 ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? programmable link function any channel can be linked with another to perform data transfer by multiple channels sequentially.
ii bus modules: intelligent dma (idma) ii-2-2 epson s1c33e08 technical manual s1c33e08 extended functions in the s 1c33e08 dma controller, some idma functions have been extended from those of the c33 std. table ii. 2.1.1 shows differences between c33 std idma and s1c33e08 idma. table ii. 2.1.1 differences between c33 std idma and s1c33e08 idma function source/destination address bit width tr ansf er counter (f or single/successive transfer) tr ansf er counter (f or block transfer) bloc k siz e setup bit width tr ansf er data siz e address decrement function with initialization control inf or mation siz e per channel control inf or mation base address s1c33e08 idma 32 bits 32 bits 20 bits 12 bits 32 bits, 16 bits, 8 bits available 4 words (128 bits) 32 bits (4-word alignment) c33 std idma 28 bits 24 bits 16 bits 8 bits 16 bits, 8 bits unavailable 3 words (96 bits) 28 bits (word alignment) note that the item layout in the control information has been changed along with this functional extension. furthermore, the control information is no longer placed in the area 0 built-in ram (a0ram).
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.2 programming control information the intelligent dma operates according to the control information prepared in ram. note that the control information must be placed in dst ram (area 3 ) or an external ram. a0 ram (area 0 ) cannot be used to store control information. the control information is 4 words (16 bytes) per channel in size, and must be located at continuous addresses beginning with the base address that is set in the software application as the starting address of channel 0. consequently, an area of 512 words (2,048 bytes) in ram is required in order for all of 128 channels to be used. note that the last 132 bytes in dst ram (area 3 ) are reserved for the debug circuits. therefore, up to 119 channels are available when using the on-chip debug functions. the following explains how to set the base address and the contents of control information. before using idma, make each the settings described below. ii.2.2.1 setting the base address set the starting address of control information (starting address of channel 0 ) to dbasel[ 15 : 0 ] (d[ 15 : 0 ]/ 0 x 301100 ) for 16 low-order bits and dbaseh[15:0] (d[15:0]/0x301102) for 16 high-order address bits. ? dbasel[15:0] : idma low-order base address bits in the idma base address register 0 (d[15:0]/0x301100) ? dbaseh[15:0] : idma high-order base address bits in the idma base address register 1 (d[15:0]/0x301102) when initially reset, the base address is set to 0x200003a0. notes : ? the control information must be placed in dst ram (area 3 ) or an external ram. a 0 ram (area 0 ) cannot be used to store control information. ? the address you set in the idma base address register must always be 4 -word units boundary address. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0 / 0 x 301105 ) = 1 ). when the register is read, the read data is indeterminate. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) ii.2.2.2 control information write the control information for the idma channels used to ram. the addresses at which the control information of each channel is placed are determined by the base address and a channel number. starting address of channel = base address + (channel number 16 [bytes]) note : the control information must be written only when the channel to be set does not start a dma transfer. if a dma transfer starts when the control information is being written to the ram, proper transfer cannot be performed. reading the control information can always be done.
ii bus modules: intelligent dma (idma) ii-2-4 epson s1c33e08 technical manual the contents of control information (4 words) in each channel are shown in the table below. table ii. 2.2.2.1 idma control information wo rd 1st 2nd 3rd 4th bit d31 d30C24 d23C18 d17C16 d15 d14C12 d11 d10C8 d7C6 d5C4 d3C1 d0 d31C12 d11C0 d31C0 d31C0 function idma link enab le 1 = enab led, 0 = disab led idma link field C data siz e control (do not set to 11.) da tsiz1 da tsiz0 setting contents 1 0 w ord (32 bits) 0 1 half-word (16 bits) 0 0 byte (8 bits) C source address control (do not set to others .) srinc2 srinc1 srinc0 setting contents 1 0 0 address decrement with initialization (address is reset in successiv e or b loc k transf er mode) 0 1 1 address increment without initialization (address is not reset) 0 1 0 address increment with initialization (address is reset in successiv e or b loc k transf er mode) 0 0 1 address decrement without initialization (address is not reset) 0 0 0 address fix ed C destination address control (do not set to others .) dsinc2 dsinc1 dsinc0 setting contents 1 0 0 address decrement with initialization (address is reset in successiv e or b loc k transf er mode) 0 1 1 address increment without initialization (address is not reset) 0 1 0 address increment with initialization (address is reset in successiv e or b loc k transf er mode) 0 0 1 address decrement without initialization (address is not reset) 0 0 0 address fix ed C tr ansf er mode (do not set to 11.) dmod1 dmod0 setting contents 1 0 bloc k transf er mode 0 1 successiv e transf er mode 0 0 single transf er mode C end-of-transf er interr upt enab le 1 = enab led, 0 = disab led tr ansf er counter (b loc k transf er mode) tr ansf er counter - 20 high-order bits (single or successiv e transf er mode) bloc k siz e (b loc k transf er mode) tr ansf er counter - 12 lo w-order bits (single or successiv e transf er mode) source address destination address name lnken lnkchn[6:0] reser ve d da tsiz[1:0] reser ve d srinc[2:0] reser ve d dsinc[2:0] reser ve d dmod[1:0] reser ve d dinten tc[19:0] blklen[11:0] sradr[31:0] dsadr[31:0] lnken: idma link enable (d 31/1 st word) if this bit remains set (= 1 ), the idma channel that is set in the idma link field is invoked after the completion of a dma transfer in this channel. dma transfers in multiple channels can be performed successively by merely triggering the first channel to be executed. there is no limit to the number of channels linked. set this link in order of the idma channels you want to be executed. if this bit is 0 , idma is completed by merely executing a dma transfer in this channel. lnkchn[6:0 ]: idma link field (d[30:24]/1 st word) if you want idma to be linked, set the channel numbers ( 0 to 127 ) to be executed next. the data in this field is valid only when lnken = 1.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 datsiz[ 1:0 ]: data size control (d[17:16]/1 st word) set the unit size of data to be transferred. table ii. 2.2.2.2 transfer data size da tsiz1 1 1 0 0 da tsiz0 1 0 1 0 t ransfer data siz e in v alid w ord (32 bits) half-word (16 bits) byte (8 bits) srinc[2:0 ]: source address control (d[14:12]/1 st word) set the source address control condition. ? srinc[ 2:0] = 000 : address fixed the source address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read from the same address. ? srinc[ 2:0] = 011 : address increment without initialization (address is not reset) the source address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been incremented during transfer does not return to the initial value. ? srinc[ 2:0] = 001 : address decrement without initialization (address is not reset) the source address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been decremented during transfer does not return to the initial value. ? srinc[ 2:0] = 010 : address increment with initialization (address is reset in successive or block transfer mode) the source address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. ? srinc[ 2:0] = 100 : address decrement with initialization (address is reset in successive or block transfer mode) the source address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. ? srinc[ 2:0 ] = other than above: settings are prohibited note : in single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. dsinc[2:0 ]: destination address control (d[10:8]/1 st word) set the destination address control condition. ? dsinc[ 2:0] = 000 : address fixed the destination address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always written to the same address. ? dsinc[ 2:0] = 011 : address increment without initialization (address is not reset) the destination address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been incremented during transfer does not return to the initial value.
ii bus modules: intelligent dma (idma) ii-2-6 epson s1c33e08 technical manual ? dsinc[ 2:0] = 001 : address decrement without initialization (address is not reset) the destination address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been decremented during transfer does not return to the initial value. ? dsinc[ 2:0] = 010 : address increment with initialization (address is reset in successive or block transfer mode) the destination address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. ? dsinc[ 2:0] = 100 : address decrement with initialization (address is reset in successive or block transfer mode) the destination address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. ? dsinc[ 2:0 ] = other than above: settings are prohibited note : in single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. dmod[1:0 ]: transfer mode (d[5:4]/1 st word) use these bits to set the desired transfer mode. the transfer modes are outlined below (to be detailed later): ? dmod[ 1:0] = 00 : single transfer mode in this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by datsiz. if data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? dmod[ 1:0] = 01 : successive transfer mode in this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 each time data is transferred. ? dmod[ 1:0] = 10 : block transfer mode in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen. if a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? dmod[ 1:0] = 11 : settings are prohibited dinten: end-of-transfer interrupt enable (d 0/1 st word) if this bit is left set (= 1 ), when the transfer counter reaches 0 , an interrupt request to the cpu is generated based on the cause-of-interrupt flag by which idma has been invoked. if this bit is 0 , no interrupt request to the cpu is generated even when the transfer counter has reached 0. tc[19:0 ]: transfer counter (d[31:12]/2 nd word) in block transfer mode, a transfer count can be specified using up to 20 bits. set this value here. in single transfer and successive transfer modes, a transfer count can be specified using up to 32 bits. set a 20 -bit high-order value here.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 blklen[11:0 ]: block size/transfer counter (d[11:0]/2 nd word) in block transfer mode, set the size of a block that is transferred in one operation (in units of datsiz). in single transfer and successive transfer modes, set an 12 -bit low-order value for the transfer count here. note : the transfer count and block size thus set is decremented according to the transfers performed. if the transfer count is set to 0, it is decremented to all fs by the first transfer performed. this means that you have set the maximum value that is determined by the number of bits available. sradr[31:0 ]: source address (d[31:0]/3 rd word) use these bits to set the starting address at the source of transfer. the content set here is updated according to the setting of srinc. dsadr[31:0 ]: destination address (d[31:0]/4 th word) use these bits to set the starting address at the destination of transfer. the content set here is updated according to the setting of dsinc. notes : ? area 0 (a0ram) and area 2 cannot be used for idma transfer and storing control information. ? since the control information is placed in ram, it can be rewritten. however, before rewriting the content of this information, make sure that no dma transfer is generated in the channel whose information you are going to rewrite.
ii bus modules: intelligent dma (idma) ii-2-8 epson s1c33e08 technical manual ii.2.3 idma invocation the triggers by which idma is invoked have the following three causes: 1 . cause of interrupt in internal peripheral circuits (hardware trigger) 2 . trigger in the software application 3. link setting enabling/disabling dma transfer the idma controller is enabled by writing 1 to the idma enable bit idmaen (d0/0x301105 ), and is ready to accept the triggers described above. however, before enabling a dma transfer, be sure to set the base address and the control information for the channel to be invoked correctly. if idmaen (d 0/0x301105 ) is set to 0 , no idma invocation request is accepted. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) idma invocation by a cause of interrupt in internal peripheral circuits some internal peripheral circuits that have an interrupt generating function can invoke idma by a cause of interrupt in that circuit. the idma channel numbers corresponding to such idma invocation are predetermined. the relationship between the causes of interrupt that have this function and the idma channels is shown in table ii. 2.3.1. table ii. 2.3.1 interrupt causes used to invoke idma p eripheral cir cuit i/o por ts high-speed dma 16-bit timers 0C5 ser ial interf ace ch.0Cch.1 a/d con ve r ter i/o por ts lcdc ser ial interf ace ch.2 spi i/o por ts or por t mux interr upt i/o por ts i 2 s cause of interrupt po rt input 0 po rt input 1 po rt input 2 po rt input 3 ch.0, end of transf er ch.1, end of transf er timer 0 compar ison b timer 0 compar ison a timer 1 compar ison b timer 1 compar ison a timer 2 compar ison b timer 2 compar ison a timer 3 compar ison b timer 3 compar ison a timer 4 compar ison b timer 4 compar ison a timer 5 compar ison b timer 5 compar ison a ch.0 receiv e b uff er full ch.0 transmit b uff er empty ch.1 receiv e b uff er full ch.1 transmit b uff er empty end of a/d con v ersion po rt input 4 po rt input 5 po rt input 6 po rt input 7 end of frame ch.2 receiv e b uff er full ch.2 transmit b uff er empty receiv e dma request tr ansmit dma request po rt input 8 / spi po rt input 9 / usb pdreq po rt input 10 / usb int po rt input 11 / dcsio po rt input 12 po rt input 13 po rt input 14 po rt input 15 i 2 s idma enable bit dep0 (d0/0x300294) dep1 (d1/0x300294) dep2 (d2/0x300294) dep3 (d3/0x300294) dehdm0 (d4/0x300294) dehdm1 (d5/0x300294) de16tu0 (d6/0x300294) de16tc0 (d7/0x300294) de16tu1 (d0/0x300295) de16tc1 (d1/0x300295) de16tu2 (d2/0x300295) de16tc2 (d3/0x300295) de16tu3 (d4/0x300295) de16tc3 (d5/0x300295) de16tu4 (d6/0x300295) de16tc4 (d7/0x300295) de16tu5 (d0/0x300296) de16tc5 (d1/0x300296) desrx0 (d6/0x300296) destx0 (d7/0x300296) desrx1 (d0/0x300297) destx1 (d1/0x300297) deade (d2/0x300297) dep4 (d4/0x300297) dep5 (d5/0x300297) dep6 (d6/0x300297) dep7 (d7/0x300297) delcdc (d1/0x30029c) desrx2 (d2/0x30029c) destx2 (d3/0x30029c) despirx (d4/0x30029c) despitx (d5/0x30029c) dep8 (d0/0x3002ae) dep9 (d1/0x3002ae) dep10 (d2/0x3002ae) dep11 (d3/0x3002ae) dep12 (d4/0x3002ae) dep13 (d5/0x3002ae) dep14 (d6/0x3002ae) dep15 (d7/0x3002ae) dei2s (d0/0x3002af) idma request bit rp0 (d0/0x300290) rp1 (d1/0x300290) rp2 (d2/0x300290) rp3 (d3/0x300290) rhdm0 (d4/0x300290) rhdm1 (d5/0x300290) r16tu0 (d6/0x300290) r16tc0 (d7/0x300290) r16tu1 (d0/0x300291) r16tc1 (d1/0x300291) r16tu2 (d2/0x300291) r16tc2 (d3/0x300291) r16tu3 (d4/0x300291) r16tc3 (d5/0x300291) r16tu4 (d6/0x300291) r16tc4 (d7/0x300291) r16tu5 (d0/0x300292) r16tc5 (d1/0x300292) rsrx0 (d6/0x300292) rstx0 (d7/0x300292) rsrx1 (d0/0x300293) rstx1 (d1/0x300293) rade (d2/0x300293) rp4 (d4/0x300293) rp5 (d5/0x300293) rp6 (d6/0x300293) rp7 (d7/0x300293) rlcdc (d1/0x30029b) rsrx2 (d2/0x30029b) rstx2 (d3/0x30029b) rspirx (d4/0x30029b) rspitx (d5/0x30029b) rp8 (d0/0x3002a c) rp9 (d1/0x3002a c) rp10 (d2/0x3002a c) rp11 (d3/0x3002a c) rp12 (d4/0x3002a c) rp13 (d5/0x3002a c) rp14 (d6/0x3002a c) rp15 (d7/0x3002a c) ri2s (d0/0x3002ad) idma ch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 these causes of interrupt are used in common for interrupt re quests and idma invocation requests. to invoke idma upon the occurrence of a cause of interrupt, set the corresponding bits of the idma request and idma enable registers shown in the table by writing 1 . then when a cause of interrupt occurs, an interrupt request to the cpu is kept pending and the corresponding idma channel is invoked. the cause-of-interrupt flag that has been set to 1 remains set until the dma transfer invoked by it is completed. if the following two conditions are met when one dma transfer is completed, an interrupt request is generated without resetting the cause-of-interrupt flag. ? the transfer counter has reached 0. ? dinten in control information is set to 1 (interrupt enabled). in this case, the idma request bit is cleared to 0 . therefore, if idma needs to be invoked when a cause of interrupt occurs next time, this register must be set up again. to prevent unwanted idma requests from being generated, this setting must be performed before enabling interrupts and after resetting the cause-of-interrupt flag. the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten in control information has been set to 0 , the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. if the idma request register bit is left reset to 0 , the relevant cause of interrupt generates an interrupt request and not an idma request. the control registers (interrupt enable register and interrupt priority register) corresponding to the cause of interrupt do not affect idma invocation. idma can be invoked even if the interrupt enable bit in itc is set to 0 (interrupt disabled). however, these register must be set to enable the interrupt when generating the interrupt after completing the dma transfer.
ii bus modules: intelligent dma (idma) ii-2-10 epson s1c33e08 technical manual idma invocation by a trigger in the software application all idma channels for which control information is set, including those corresponding to causes of interrupt described above, can be invoked by a trigger in the software application. when the idma channel number to be invoked ( 0 to 127 ) is written to dchn[6:0 ] (d[6:0]/0x301104 ) and dstart (d 7/0x301104 ) is set to 1 after setting idmaen (d0/0x301105 ) to 1 , the specified idma channel starts a dma transfer. ? dchn[6:0] : idma channel number set-up bits in the idma start register (d[6:0]/0x301104) ? dstart : idma start control bit in the idma start register (d7/0x301104) dstart remains set (= 1 ) during a dma transfer and is reset to 0 in hardware when one dma transfer operation is completed. do not modify these bits during a dma transfer. if dinten is set to 1 (interrupt enabled), a cause of interrupt for the completion of idma transfer is generated when one dma transfer is completed. idma invocation by link setting if lnken in the control information is set to 1 (link enabled), the idma channel that is set in the idma link field lnkchn is invoked successively after a dma transfer in the link-enabled channel is completed. the interrupt request by the first channel is generated after transfers in all linked channels are completed if the interrupt conditions are met. to generate an interrupt at the end of an idma transfer, the dinten (end-of-transfer interrupt enable) bits in the idma control information for the first idma channel to be invoked and all the channels to be linked must be set to 1. idma invocation request during a dma transfer an idma invocation request to another channel that is generated during a dma transfer is kept pending until the dma transfer that was being executed at the time is completed. since an invocation request is not cleared, new requests will be accepted when the dma transfer under execution is completed. an idma invocation request to the same channel cannot be accepted while the channel is executing a dma transfer because the same cause of interrupt is used. therefore, an interval longer than the dma transfer period is required when invoking the same channel. idma invocation request when dma transfer is disabled an idma invocation request generated when idmaen (d 0/0x301105 ) is 0 (dma transfer disabled) is kept pending until idmaen (d 0/0x301105 ) is set to 1 . since an invocation request is not cleared, it is accepted when dma transfer is enabled. simultaneous generation of a software trigger and a hardware trigger when a software trigger and the hardware trigger for the same channel are generated simultaneously, the software trigger starts idma transfer. the idma transfer by the hardware trigger is executed after the dma transfer by the software trigger is completed.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.4 operation of idma idma has three transfer modes, in each of which data transfer operates differently. furthermore, a cause of interrupt is processed differently depending on the type of trigger. idma supports only dual-address transfers. it does not support single-address transfers. the following describes the operation of idma in each transfer mode and how a cause of interrupt is processed for each type of trigger. ii.2.4.1 single transfer mode the channels for which dmod in control information is set to 00 operate in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by datsiz. if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of idma in single transfer mode is shown by the flow chart in figure ii. 2.4.1.1. start end calculates address of control information loads channel control information transfers one unit of data transfer counter - 1 saves channel control information idma interrupt processing (if interrupt is enabled) transfer counter = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e fn (4 words) :n = 1C4 n trigger y a b1 b2 b3 b4 c d e f1 f2 f4 f3 figure ii.2.4.1.1 operation flow in single transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and the transfer c ounter is decremented. (6 ) the modified control information is written to ram. (7 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) ii-2-12 epson s1c33e08 technical manual ii.2.4.2 successive transfer mode the channels for which dmod in control information is set to 01 operate in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of idma in successive transfer mode is shown by the flow chart in figure ii. 2.4.2.1. start end calculates address of control information loads channel control information transfers one unit of data transfer counter - 1 saves channel control information idma interrupt processing (if interrupt is enabled) transfer counter = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e gn (4 words) :n = 1C4 n trigger y a b1 b2 b3 b4 c1 d1 e1 cn dn en f g1 g2 g3 g4 restores initial values to address ? f ? : according to srinc/dsinc settings figure ii.2.4.2.1 operation flow in successive transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and the transfer c ounter is decremented. (6 ) steps (3) to (5) are repeated until the transfer counter reaches 0. (7 ) if srinc and/or dsinc are 010 or 100 , the address is recycled to the initial value. (8 ) the modified control information is written to ram. (9 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.4.3 block transfer mode the channels for which dmod in control information is set to 10 operate in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen. if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of idma in block transfer mode is shown by the flow chart in figure ii. 2.4.3.1. start end calculates address of control information loads channel control information transfers one unit of data block size - 1 restores initial values to block size and address ? idma interrupt processing (if interrupt is enabled) block size = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e 1-block transfer f g n trigger y a b1 b2 b4 b3 c1 d1 e1 cn dn en f g h1 h2 h4 h3 transfer counter - 1 saves channel control information transfer counter = 0 hn (4 words) :n = 1C4 n y ? : according to srinc/dsinc settings figure ii.2.4.3.1 operation flow in block transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and blklen is decreme nted. (6 ) steps (3) to (5) are repeated until blklen reaches 0. (7 ) if srinc and/or dsinc are 010 or 100 , the address is recycled to the initial value. (8 ) the transfer counter is decremented. (9 ) the modified control information is written to ram. (10 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) ii-2-14 epson s1c33e08 technical manual ii.2.4.4 cause-of-interrupt processing by trigger type when invoked by a cause of interrupt the cause-of-interrupt flag by which idma has been invoked remains set even during a dma transfer. if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, the cause of interrupt that has invoked idma is not reset and an interrupt request is generated. at the same time, the idma request bit is cleared to 0 . the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. 2 1 0 trigger by cause of interrupt data transfer transfer counter dinten idma request bit idma enable bit cause-of-interrupt flag interrupt request 1 0 figure ii.2.4.4.1 operation when invoked by cause of interrupt when idma is invoked by a cause of interrupt, the idma cause-of-interrupt flag fidma (d 4/0x300281 ) will not be set. ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) when invoked by a software trigger if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, fidma (d4/0x300281) is set, thereby generating an interrupt request. if the transfer counter is not 0 or dinten = 0 (interrupt disabled), fidma (d4/0x300281) is not set. if the cause-of-interrupt flag for the same channel is set during a software-triggered transfer, the idma invocation request by that cause-of-interrupt flag is kept pending. however, the cause-of-interrupt flag will be reset when the current execution is completed, so there will be no dma transfer by the cause-of-interrupt flag. 2 1 0 software trigger data transfer transfer counter dinten fidma (d4/0x300281) interrupt request 1 0 figure ii.2.4.4.2 operation when invoked by software trigger
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.5 linking if the idma channel number to be executed next is set in the idma link field lnkchn of control information and lnken is set to 1 (link enabled), dma successive transfer in that idma channel can be performed. an example of link setting is shown in figure ii. 2.5.1. ch.3 trigger after transfer tc = 0 lnken = 1 lnkchn = 5 dmod = 01 dinten = 1 tc = 1024 ch.5 tc = 7 lnken = 1 lnkchn = 7 dmod = 00 dinten = 1 tc = 8 ch.7 tc = 0 lnken = 0 lnkchn = 9 dmod = 10 dinten = 1 tc = 1 figure ii.2.5.1 example of link setting for the above example, idma operates as described below. for trigger in hardware (1 ) the idma channel 3 is invoked by a cause of interrupt and the dma transfer that is set is performed. since the idma is operating in successive transfer mode and the transfer counter is decremented to 0 and dinten is set to 1, the cause-of-interrupt flag by which the channel 3 has been invoked remains set. (2 ) next, a dma transfer is performed via the linked idma channel 5 . channel 5 is set for single transfer mode and the transfer counter in this transfer is decremented by 1. (3 ) finally, a dma transfer in idma channel 7 is performed. although the channel 7 is set for block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. (4 ) since the cause-of-interrupt flag that has invoked idma channel 3 in (1 ) remains set, an interrupt is generated when the idma transfer (channel 7 ) in (3 ) is completed. the transfer result does not affect the cause-of- interrupt flag of channel 3. to generate an interrupt at the end of an idma transfer, the dinten (end-of-transfer interrupt enable) bits in the idma control information for the first idma channel to be invoked and all the channels to be linked must be set to 1. for trigger in the software application (1 ) the idma channel 3 is invoked by a software trigger dstart (d7/0x301104 ) and the dma transfer that is set is performed. since the idma is operating in successive transfer mode and the transfer counter is decremented to 0 and dinten is set to 1 , the idma cause-of-interrupt flag fidma (d4/0x300281 ) is set when the transfer is completed. ? dstart : idma start control bit in the idma start register (d7/0x301104) ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) (2 ) next, a dma transfer is performed in the linked idma channel 5 . the channel 5 is set for the single transfer mode and the transfer counter in this transfer is decremented by 1. (3 ) finally, a dma transfer in idma channel 7 is performed. although channel 7 is set for the block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1 . the completion of this transfer also causes fidma (d4/0x300281 ) to be set to 1. however, fidma (d 4/0x300281) has already been set when the transfer is completed in (1 ) above. (4 ) since fidma (d4/0x300281 ) is set, an interrupt request is generated here. in cases when idma has been invoked by a trigger in the software application, if the transfer counter in any one of the linked channels is decremented to 0 and dinten for that channel is set to 1 , an interrupt request for the completion of idma transfer is generated when a transfer operation in each of the linked channels is completed. the channel in which an interrupt request has been generated can be verified by reading out the transfer counter. transfer operations in each channel are performed as described earlier.
ii bus modules: intelligent dma (idma) ii-2-16 epson s1c33e08 technical manual ii.2.6 interrupt function of intelligent dma idma can generate an interrupt that causes invocation of idma and an interrupt for the completion of idma transfer itself. interrupt when invoked by a cause of interrupt if the corresponding bits of the idma request and interrupt enable registers are left set (= 1 ), assertion of an interrupt request is kept pending even when the enabled cause of interrupt has occurred and the idma channel assigned to that cause of interrupt is invoked. if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, the cause of interrupt that has invoked idma is not reset and an interrupt request is generated. at the same time, the idma request bit is cleared to 0 . the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. when idma is invoked by a cause of interrupt, the idma cause-of-interrupt flag fidma (d 4/0x300281 ) will not be set. for details about the causes of interrupt that can be used to invoke idma and the interrupt control registers, refer to the descriptions of the peripheral circuits in this manual. note that the priority levels of causes of interrupt are set by the interrupt priority register. refer to section iii. 2, interrupt controller (itc). however, when compared between idma and interrupt requests, idma is given higher priority over the other. consequently, even when a cause of interrupt occurring during an idma transfer has higher priority than the cause of interrupt that invoked the idma transfer, an interrupt request for it or a new idma invocation request is not accepted until after the current idma transfer is completed. software-triggered interrupts if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer operation is completed, fidma (d 4/0x300281 ) is set, thereby generating an interrupt request. if the transfer counter is not 0 or dinten = 0 (interrupt disabled), fidma (d4/0x300281) is not set. idma interrupt control register in the interrupt controller the following control bits are used to control an interrupt for the completion of idma transfer: ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) ? eidma : idma interrupt enable bit in the dma interrupt enable register (d4/0x300271) ? pdm[2:0] : idma interrupt level bits in the idma interrupt priority register (d[2:0]/0x300265) when a dma transfer in the idma channel invoked by a trigger in the software application or subsequent link is completed and the transfer counter is decremented to 0 , the cause-of-interrupt flag for the completion of idma transfer is set to 1 . however, this requires as a precondition that interrupt be enabled (dinten = 1 ) in the control information for that channel. if the interrupt enab le register bit remains set (= 1) when the flag is set, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit cleared (= 0 ). use the interrupt priority register to set interrupt priority levels (0 to 7 ). an interrupt request to the cpu is accepted on condition that no other interrupt request of higher priority is generated. furthermore, it is only when the psr's ie bit = 1 (interrupt enabled) and the set value of il is smaller than the idma interrupt level which is set by the interrupt priority register that the cpu actually accepts an idma interrupt request. for details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to section iii.2, interrupt controller (itc). trap vector the trap vector address for an interrupt upon completion of idma transfer by default is set to 0xc00068. the trap table base address can be changed using the ttbr registers.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.7 details of control registers table ii. 2.7.1 list of idma registers address 0x00301100 0x00301102 0x00301104 0x00301105 function sets 16 low-order bits of idma base address. sets 16 high-order bits of idma base address. invokes an idma channel. enables idma. register name idma base address register 0 (pidmabase) idma base address register 1 idma start register (pidma_start) idma enable register (pidma_en) siz e 16 16 8 8 the following describes each idma control register. the idma control registers are mapped in the 16 -bit device area from 0x301100 to 0x301105 , and can be accessed in units of half-words or bytes. note : when setting the idma control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: intelligent dma (idma) ii-2-18 epson s1c33e08 technical manual 0x301100: idma base address register 0 (pidmabase) 0x301102: idma base address register 1 name address register name bit function setting init. r/w remarks dbasel15 dbasel14 dbasel13 dbasel12 dbasel11 dbasel10 dbasel9 dbasel8 dbasel7 dbasel6 dbasel5 dbasel4 dbasel3 dbasel2 dbasel1 dbasel0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address low-order 16 bits (initial value: 0x200003a0) 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 r/w fix at 0. 00301100 (hw) idma base address register 0 (pidmabase) dbaseh15 dbaseh14 dbaseh13 dbaseh12 dbaseh11 dbaseh10 dbaseh9 dbaseh8 dbaseh7 dbaseh6 dbaseh5 dbaseh4 dbaseh3 dbaseh2 dbaseh1 dbaseh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address high-order 16 bits (initial value: 0x200003a0) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301102 (hw) idma base address register 1 specify the starting address of the control information to be placed in ram. at initial reset, the base address is set to 0x200003a0. d[15:0]/0x301100 dbasel[15:0]: idma low-order base address bits use dbasel to set the 16 low-order bits of the base address. d[15:0]/0x301102 dbaseh[15:0]: idma high-order base address bits use dbaseh to set the 16 high-order bits of the base address. in the s 1c33e08 idma, the dbaseh[15:12 ] bits have been added to extend the base address into 32 bits. notes : ? the control information must be placed in dst ram (area 3 ) or an external ram. a 0 ram (area 0 ) cannot be used to store control information. ? the address you set in the idma base address registers must always be 4 -word units boundary address. ? these registers cannot be read or written in bytes. the registers must be accessed in words for read/write operations to address 0x301100 , or in half-words for read/write operations to addresses 0x301100 and 0x301102 . write operations in half-words must be performed in order of 0x301100 and 0x301102 . read operations in half-words may be performed in any order. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0 / 0 x 301105 ) = 1 ). when the register is read, the read data is indeterminate.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301104: idma start register (pidma_start) name address register name bit function setting init. r/w remarks 0 to 127 dstart dchn6 dchn5 dchn4 dchn3 dchn2 dchn1 dchn0 d7 d6 d5 d4 d3 d2 d1 d0 idma start idma channel number 1 idma start 0 stop 0 0 r/w r/w 00301104 (b) idma start register (pidma_start) d7 dstart: idma start control bit use this bit for software trigger and for monitoring the operation of idma. 1 (w): start idma 0 (w): has no effect 1 (r): operating (only when invoked by software trigger) 0 (r): idle (default) when dstart is set to 1 , it functions as a software trigger, invoking the idma channel that is set in the dchn register. d[6:0] dchn[6:0]: idma channel number setting bits set the channel numbers ( 0 to 127 ) to be invoked by software trigger. (default: 0) note : do not start an idma transfer and change the idma channel number simultaneously. when setting dchn[6:0], write 0 to dstart.
ii bus modules: intelligent dma (idma) ii-2-20 epson s1c33e08 technical manual 0x301105: idma enable register (pidma_en) name address register name bit function setting init. r/w remarks C C idmaen d7C1 d0 reserved idma enable (for software trigger) 1 enabled 0 disabled C 0 C r/w 0 when being read. 00301105 (b) idma enable register (pidma_en) d[7:1] reserved d0 idmaen: idma enable bit enable a idma transfer. 1 (r/w): enable 0 (r/w): disable (default) idma transfer is enabled by writing 1 to this bit and is disabled by writing 0.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.8 precautions ? the control information must be placed in dst ram (area 3 ) or an external ram. area 0 (a0 ram) and area 2 cannot be used for idma transfer and storing control information. ? the address you set in the idma base address registers must always be 4 -word units boundary address. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0/0x301105 ) = 1 ). when the register is read, the read data is indeterminate. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) ? do not start an idma transfer and change the idma channel number simultaneously. when setting dchn[6:0] (d[6:0]/0x301104), write 0 to dstart (d7/0x301104). ? dchn[6:0] : idma channel number set-up bits in the idma start register (d[6:0]/0x301104) ? dstart : idma start control bit in the idma start register (d7/0x301104) ? since the control information is placed in ram, it can be rewritten. however, before rewriting the content of this information, make sure that no dma transfer is generated in the channel whose information you are going to rewrite. ? since the c33 pe core performs look-ahead operations, do not specify another channel immediately after a software trigger has invoked a channel. ? be sure to disable the idma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the idma is enabled.
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ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3 sram controller (sramc) ii.3.1 overview of the sramc the sram controller (sramc) is a bus module connected to the cpu_ahb bus. the sramc manages the external memory space by dividing it into 19 areas. this module controls external bus signals according to bus conditions set for each area as it accesses the connected memor y or i/o device. the sramc functions and features are outlined below. ? supports a 32 -bit address bus and data bus. ? controls external memory space as 19 divided areas (areas 4 to 22). ? allows various conditions (e.g., device type, device size, number of wait cycles) to be set for each area. ? outputs 8 chip-enable signals (#ce4 to #ce11 ) corresponding to each external area. ? supports two interface modes: a0 and bsl (with bsl mode for external memory only). ? allows sram, rom, or flash memory to be connected directly to the external bus. ? allows wait states to be inserted from the external #wait pin (for sram type only). ? little endian
ii bus modules: sram controller (sramc) ii-3-2 epson s1c33e08 technical manual ii.3.2 sramc pins table ii. 3.2.1 lists the pins used by the sramc. table ii. 3.2.1 sramc pin list pin name a0/ #bsl a[24:1] d[15:0] #ce11 #ce10 #ce9 #ce8 #ce7 #ce6 #ce5 #ce4 #rd #wrl/ #wr #wrh/ #bsh bclk #w ait boo t[1:0] i/o o o i/o o i/o o o o o o o o o o o i i function address signal output pin / lo w-order b yte b us strobe signal output pin address signal output pins (e xter nal address b us) data signal input/output pins (e xter nal data b us) area 11/12 chip enab le signal output pin area 10/13/20 chip enab le signal output pin / boot mode select pin area 9/22 chip enab le signal output pin area 8/21 chip enab le signal output pin area 7/19 chip enab le signal output pin area 6/17/18 chip enab le signal output pin area 5/15/16 chip enab le signal output pin area 4/14 chip enab le signal output pin read signal output pin lo w-order b yte wr ite signal output pin (when accessing a0 interf aced area) / wr ite signal output pin (when accessing bsl interf aced area) high-order b yte wr ite signal output pin (when accessing a0 interf aced area) / high-order b yte b us strobe signal output pin (when accessing bsl interf aced area) bus cloc k output pin exter nal w ait request input pin boot mode select pins (boo t0 is not av ailab le in the qfp24-144pin pac kage model) notes : ? some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the sramc. before the sramc signals assigned to these pins can be used, the functions of these pins must be switched for the sramc by setting each corresponding port function select register. for details on how to switch over the pin functions, see section i. 3.3, switching over the multiplexed pin functions. ? the bus control signals can be pulled high or forcibly driven low in software. for details on how to control, see section iii. 4, misc registers.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.3 external memory area (areas 4 , 5 , 7 to 22) the sramc supports an external memory space, which is divided into 19 areas as shown in figure ii.3.3.1. area 13 0x02ff ffff 0x0200 0000 area 12 ( ? 1) 0x01ff ffff 0x0180 0000 area 11 ( ? 1) 0x017f ffff 0x0100 0000 area 10 0x00ff ffff 0x00c0 0000 area 9 ( ? 1) 0x00bf ffff 0x0080 0000 area 8 0x007f ffff 0x0060 0000 area 7 ( ? 1, ? 2) 0x005f ffff 0x0040 0000 area 6 0x003f ffff 0x0030 0000 (reserved for internal peripherals) area 5 0x002f ffff 0x0020 0000 area 4 ( ? 1) 0x001f ffff 0x0010 0000 area 15 0x05ff ffff 0x0400 0000 area 14 ( ? 1) 0x03ff ffff 0x0300 0000 external memory 16m bytes external memory 8m bytes external memory 8m bytes external memory 4m bytes external memory 4m bytes external memory 2m bytes external memory 2m bytes external memory 1m bytes external memory 1m bytes area 18 0x0fff ffff 0x0c00 0000 area 17 0x0bff ffff 0x0800 0000 area 16 0x07ff ffff 0x0600 0000 external memory 64m bytes area 19 ( ? 1, ? 2) 0x13ff ffff 0x1000 0000 external memory 64m bytes area 20 0x23ff ffff 0x2000 0000 external memory 64m bytes area 21 0x43ff ffff 0x4000 0000 external memory 64m bytes area 22 ( ? 1, ? 2) 0x83ff ffff 0x8000 0000 external memory 64m bytes external memory 64m bytes external memory 32m bytes external memory 32m bytes external memory 16m bytes #ce4 #ce5 #ce6 ( ?3) #ce7 ( ?4) #ce 8 #ce9 #ce10 #ce11 ? 1 usable as memory space for smartmedia (nand flash), compactflash, or pc card. ? 2 usable as the sdram area. ? 3 external memory cannot be accessed. ? 4 area 22 is assigned to #ce9 in default settings. note that area 22 will be reassigned to #ce7 when the sdramc is enabled. figure ii.3.3.1 external memory space of the s1c33e08 areas 4, 5, 7 to 22 comprise an external memory area accessible from the sramc, to which external memory devices may be connected. the device type and size, and number of wait cycles may be set for each of these areas to be accessed.
ii bus modules: sram controller (sramc) ii-3-4 epson s1c33e08 technical manual ii.3.3.1 chip enable signals the s 1c33e08 provides 25 bits of an external address bus, 16 bits of an external data bus, and eight chip-enable pins (#ce4 to #ce11 ), allowing access to the 512mb address space. two or more areas are assigned to each chip-enable signal. table ii. 3 . 3 . 1 . 1 shows the relationship between the chip- enable pins and corresponding areas. table ii. 3.3.1.1 relationship between chip-enable pins and corresponding areas #ce pin #ce4 #ce5 #ce6 #ce7 #ce8 #ce9 #ce10 #ce11 corresponding area areas 4, 14 areas 5, 15, 16 areas 17, 18 areas 7, 19 areas 8, 21 areas 9, 22 areas 10, 13, 20 areas 11, 12 area area 4 area 5 area 17+18 area 7 area 8 area 9 area 10 area 11+12 siz e 1mb 1mb 128mb 2mb 2mb 4mb 4mb 16mb area area 14 area 15+16 C area 19 area 21 area 22 area 13 C siz e 16mb 64mb C 64mb 64mb 64mb 16mb C area C C C C C C area 20 C siz e C C C C C C 64mb C usable size of area in continuous address rang e the #ce x signal also becomes active when an address in any corresponding area is accessed. area 6 is allocated to the i/o area for s1c33e08 ip and peripheral circuits. although area 6 is one of external memory areas, external memory cannot be accessed. ii.3.3.2 area condition settings bus access conditions can be set by area for each #ce x signal. therefore, the same conditions for two or more areas accommodated by the respective #ce x signals will be set. this section describes the parameters to be set individually for each area and the relevant control bits. the sramc control registers are initialized by an initial reset. these registers should be set up back again in software to suit the external device configuration or specification as required. for details of bus cycle operation, see section ii. 3.6, bus access timing chart. note : the control register and control bit configurations are the same for all #ce4 to #ce11 areas. the control bit names begin with ce4 to ce11 to indicate the relevant areas, which in the description below are commonly represented by ce x for all areas. table ii. 3.3.2.1 area parameter settings setup item de vice type (#ce4C#ce11) de vice siz e (#ce4C#ce9, #ce11) static w ait cycle (#ce4C#ce11) #ce setup time (#ce4, #ce11) output disab le time (#ce9) content bsl a0 16 bits 8 bits inser t 7 w ait cycles : inser t 0 w ait cycles no setup time +1 bclk 7 cycles : 0 cycles contr ol bit settings ce x type = 1 ce x type = 0 (def ault) ce x size[1:0] = 01 (def ault) ce x size[1:0] = 10 ce x w ait[2:0] = 111 (def ault) : ce x w ait[2:0] = 000 ce x stup = 1 ce x stup = 0 (def ault) ce9hold[2:0] = 111 : ce9hold[2:0] = 000 (def ault) endian mode the s 1c33e08 supports little endian mode only. device type the sramc incorporates an sram-type bus interface, allowing a 0 (default) or bsl to be selected as the device type. to use a bsl-type device in the #ce x area, set ce xtype (d x - 4/0x30150c) to 1. ? ce x type : #ce x device type select bit in the device type setup register (d x - 4/0x30150c) table ii. 3.3.2.2 lists the bus control signal pins used in each device type.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 3.3.2.2 bus control signal pins used in a0 and bsl modes pin name #ce x #rd a0/#bsl #wrl/#wr #wrh/#bsh a0 (default) #ce x #rd unused #wrl #wrh bsl #ce x #rd #bsl #wr #bsh device size use ce xsize[1:0] (0x301508 ) to select a device size. ? ce4size[1:0] : #ce4 device size select bits in the device size setup register (d[1:0]/0x301508) ? ce5size[1:0] : #ce5 device size select bits in the device size setup register (d[3:2]/0x301508) ? ce6size[1:0] : #ce6 device size select bits in the device size setup register (d[5:4]/0x301508) ? ce7size[1:0] : #ce7 device size select bits in the device size setup register (d[7:6]/0x301508) ? ce8size[1:0] : #ce8 device size select bits in the device size setup register (d[9:8]/0x301508) ? ce9size[1:0] : #ce9 device size select bits in the device size setup register (d[11:10]/0x301508) ? ce11size[1:0] : #ce11 device size select bits in the device size setup register (d[15:14]/0x301508) table ii. 3.3.2.3 selection of device sizes ce x size1 1 1 0 0 ce xsize0 1 0 1 0 de vice siz e reser ve d 8 bits 16 bits reser ve d connected data bu s C d[7:0] d[15:0] C at an initial reset, the device size is initialized to 16 bits. note : the device size of the #ce10 area is determined by the contents in address 0xc00000 at system boot. the device size is set to 16 bits when the lsb of the 0xc00000 contents is 0 or 8 bits when it is 1. static wait cycle if the number of static wait cycles is specified, the chip enable and read/write signals are always prolonged for the number of specified cycles when the area is accessed. set up the wait cycle according to the specifications of the device connected to the area using ce x wait[2:0] (0x301504). ? ce4wait[2:0] : number of #ce4 static wait cycles setup bits in the wait control register (d[2:0]/0x301504) ? ce5wait[2:0] : number of #ce5 static wait cycles setup bits in the wait control register (d[6:4]/0x301504) ? ce6wait[2:0] : number of #ce6 static wait cycles setup bits in the wait control register (d[10:8]/0x301504) ? ce7wait[2:0] : number of #ce7 static wait cycles setup bits in the wait control register (d[14:12]/0x301504) ? ce8wait[2:0] : number of #ce8 static wait cycles setup bits in the wait control register (d[18:16]/0x301504) ? ce9wait[2:0] : number of #ce9 static wait cycles setup bits in the wait control register (d[22:20]/0x301504) ? ce10wait[2:0] : number of #ce10 static wait cycles setup bits in the wait control register (d[26:24]/0x301504) ? ce11wait[2:0] : number of #ce11 static wait cycles setup bits in the wait control register (d[30:28]/0x301504) table ii. 3.3.2.4 setting the static wait cycle ce x w ait2 1 1 1 1 0 0 0 0 number of wait cyc les 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle no w ait cycle ce x w ait1 1 1 0 0 1 1 0 0 ce x w ait0 1 0 1 0 1 0 1 0 at initial reset, the static wait conditions for all external areas are set to 7 cycles. the area to which an sram device is connected allows dynamic wait control using the #wait pin in addition to the static wait control. for details of bus cycle operation including wait cycles, see section ii. 3.6, bus access timing chart.
ii bus modules: sram controller (sramc) ii-3-6 epson s1c33e08 technical manual #ce4/#ce11 setup time normally a #ce signal is asserted one bclk clock cycle before the read/write signal becomes active. for the #ce 4 and #ce11 signals, this setup time can be removed to assert the #ce and read/write signals simultaneously. set ce xstup (d1, d2/0x301500) to 1 to remove the #ce setup time. ? ce4stup : #ce4 setup time select bit in the bclk and setup time control register (d1/0x301500) ? ce11stup : #ce11 setup time select bit in the bclk and setup time control register (d2/0x301500) at initial reset, #ce 4 and #ce11 signals are configured with one bclk setup time. for the bus cycle operations with or without a setup time, see section ii. 3.6, bus access timing chart. #ce9 output disable time in cases when a device having a long output disable time is connected, if a read cycle for that device is followed in the next access, contention for the data bus may occur. (due to the fact the read device's data bus is not placed in the high-impedance state.) the output disable time is provided to prevent such a data bus contention. this is accomplished by inserting a specified number of output disable cycles between a read cycle and the next bus operation. however, this setting is effective only for the #ce 9 area. the output disable time affects bus control signals such as #rd and #wrl/#wrh. check the specifications of the device to be connected before setting the output disable time. use ce 9hold[2:0] (d[6:4]/0x301500) to set the #ce9 output disable time. ? ce9hold[2:0] : #ce9 output disable time setup bits in the bclk and setup time control register (d[6:4]/0x301500) table ii. 3.3.2.5 setting the #ce9 output disable time ce9hold2 1 1 1 1 0 0 0 0 output disable cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle none ce9hold1 1 1 0 0 1 1 0 0 ce9hold0 1 0 1 0 1 0 1 0 at initial reset, the disable delay time is initialized to none (0 cycles). the following shows the conditions under which the output disable cycle is inserted. ? the output disable cycle is always inserted during read access. ? for read access where data size > device size, the output disable cycle is only inserted during the last access. ? no output disable cycle is inserted during write access. ? no output disable cycle is inserted during consecutive accesses to the same area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.4 connection of external devices and bus operation ii.3.4.1 connecting external devices the following shows an example of connecting the s 1c33e08 and sram. s1c33e08 a[n:0] d[7:0] #ce x #rd #wrl sram a[n:0] i/o[7:0] #ce #oe #we figure ii.3.4.1.1 example of 8-bit sram connection with 8 -bit device size s1c33e08 a[n:1] d[15:0] #ce x #rd #wrl #wrh sram a[n-1:0] i/o[15:0] #ce #oe #wel #weh s1c33e08 a[n:1] d[15:0] #ce x #rd #wr #bsl #bsh sram a[n-1:0] i/o[15:0] #ce #oe #we #lb #ub figure ii.3.4.1.2 example of 16-bit sram connection with 16 -bit device size ii.3.4.2 data configuration in memory the s 1c33e08 sramc handles byte (8 -bit), halfword (16 -bit), and word (internal 32 -bit) data. to access data in memory, addresses aligned to the boundary of the data size must be specified. specifying other addresses generates address misaligned exceptions. instructions (e.g., stack manipulating and branch instructions) that rewrite the content of the stack pointer (sp) or program counter (pc) forcibly alter the address specified to a boundary address to prevent address misaligned exceptions. for details of address misaligned exceptions, refer to the c 33 pe core manual. table ii. 3.4.2.1 shows where each type of data is located in memory. table ii. 3.4.2.1 data locations in memory data type byte halfword w ord location byte boundar y (all addresses) halfword boundar y (a[0] = 0) w ord boundar y (a[1:0] = 0b00) all halfword and word data in memory are accessed in little endian mode. to increase memory efficiency, try locating the same type of data at contiguous addresses to reduce blank areas created by positioning at boundary addresses as much as possible.
ii bus modules: sram controller (sramc) ii-3-8 epson s1c33e08 technical manual ii.3.4.3 external bus operation the internal data bus size in the s 1c33e08 is 32 bits. note, however, that it has 16 external bus pins d[15:0 ]. depending on the device size and data size of the instruction executed, two or more bus operations may occur. table ii. 3.4.3.1 shows bus operation in a0 and bsl modes. for details on how to connect memory, see section ii. 3.4.1, connecting external devices. table ii. 3.4.3.1 bus operation de vice siz e 8 bits 16 bits data siz e byte half word w ord byte half word w ord r/w w r w r w r w r w r w r v alid signal #wrl #rd #wrl #rd #wrl #rd #wrl #wrh #rd #wrh #wrl #rd #wrh #wrl #rd d[15:8] pins C C C C C C C C C C C C C C C d[7:0] C d[7:0] d[7:0] pins d[7:0] d[7:0] d[7:0] d[15:8] d[7:0] d[15:8] d[7:0] d[15:8] d[23:16] d[31:24] d[7:0] d[15:8] d[23:16] d[31:24] d[7:0] C d[7:0] C access count 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1 1 1 1 1 1 1st 2nd 1st 2nd a1 ? ? ? ? ? ? 0 0 1 1 0 0 1 1 ? ? ? ? ? ? 0 1 0 1 a0 ? ? 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16] v alid signal C C C C C C #wr #bsl #wr #bsh #rd #bsl #rd #bsh #wr #bsh #bsl #rd #bsh #bsl #wr #bsh #bsl #rd #bsh #bsl d[15:8] pins C C C C C C C C C C C C C C C d[7:0] C d[7:0] d[7:0] pins C C C C C C C C C C C C C C d[7:0] C d[7:0] C d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16] a0 mode bsl mode
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.5 sramc operating clock and bus clock ii.3.5.1 operating clock of the sramc the sramc is clocked by the sramc_clk and sramc_sapb_clk clocks (= mclk) generated by the cmu. the bus control signals are generated synchronously with sramc_clk. the sramc_sapb_clk is used for the sramc control registers. for details on how to set and control the sramc operating clocks, see section iii. 1, clock management unit (cmu). controlling supply of the sramc operating clock the sramc operating clocks are supplied to the sramc with default settings. each clock supply can be controlled in the cmu. use the respective control bits to turn off any unnecessary clock supplies to reduce the amount of power consumed on the chip. 1 . sramc_sapb_clk the sramc_sapb_clk is used to operate the sramc control registers. to setup the registers, this clock is required. after the registers are set up, the clock supply can be stopped to reduce power consumption by setting sramsapb_cke (d7/0x301b04) to 0. ? sramsapb_cke : sramc sapb i/f clock control bit in the gated clock control register 1 (d7/0x301b04) 2. sramc_clk the sramc_clk is used for the sram interface. to access the external memories/devices and the peripheral control registers in area 6 , this clock is required. so this clock cannot be stopped in normal operation mode. however, the clock supply can be stopped in halt mode. by setting sramc_hcke (d26/0x301b04 ) to 0 , the sramc_clk stops when the cpu enters halt mode and it resumes when the cpu exits halt mode. ? sramc_hcke : sramc clock control (halt) bit in the gated clock control register 1 (d26/0x301b04) clock state in standby mode the supply of the sramc operating clock stops depending on the type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. it can be stopped by setting the cmu register. sleep mode: the clock supply stops. therefore, the sramc also stops operating in sleep mode.
ii bus modules: sram controller (sramc) ii-3-10 epson s1c33e08 technical manual ii.3.5.2 generation of the bus clock the sramc divides sramc_clk by a specified number to generate the bus clock (bclk). this divide-by ratio is set using the control bits shown below. setting the bus clock for areas other than #ce 9 ? bclk : bclk divide control bit in the bclk and setup time control register (d0/0x301500) setting the bus clock for the #ce 9 area ? ce9bclk : #ce9 area bclk divide control bit in the bclk and setup time control register (d7/0x301500) table ii. 3.5.2.1 bclk (sramc_clk divide-by ratio) settings bclk/ce9bclk 1 0 bclk frequenc y sramc_clk 1/2 sramc_clk 1 when initially reset, the bclk clock is set to sramc_clk 1/2. ii.3.5.3 external output of the bus clock the bclk output is an extended port function. therefore, before bclk can be output to external devices, the pin function must be switched for bclk output by using the function select register for the corresponding port. for details of the pins assigned to the bclk output function and how to switch the pin functions, see section i. 3.3, switching over the multiplexed pin functions.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6 bus access timing chart ii.3.6.1 sram read/write timings with no external #wait 1 . sram read/write timings with no static wait cycles [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid figure ii.3.6.1.1 sram read timing with no static wait cycle bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid figure ii.3.6.1.2 sram write timing with no static wait cycle
ii bus modules: sram controller (sramc) ii-3-12 epson s1c33e08 technical manual 2 . sram read/write timings with static wait cycles [example settings] device size: 16 bits number of static wait cycles: 2 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid static wait cycle figure ii.3.6.1.3 sram read timing with static wait cycle bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid static wait cycle figure ii.3.6.1.4 sram write timing with static wait cycle
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6.2 sram read/write timings with external #wait a wait cycle can be inserted from the #wait pin only for sram-type devices. the external #wait signal is sampled on the rising edges of bclk at one clock before the read or write signal goes high. a wait state is entered while the #wait signal is sampled active (low), and subsequent operation resumes when the #wait signal is sampled inactive (high). [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid wait cycle figure ii.3.6.2.1 sram read timing with external #wait bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid wait cycle figure ii.3.6.2.2 sram write timing with external #wait
ii bus modules: sram controller (sramc) ii-3-14 epson s1c33e08 technical manual ii.3.6.3 sram read/write timings with #ce4/#ce11 setup time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: +1 bclk bclk a[24:0] #ce4/11 #rd d[15:0] #wait valid valid figure ii.3.6.3.1 sram read timing with #ce4/#ce11 setup time bclk a[24:0] #ce4/11 #wr ? d[15:0] #wait valid valid figure ii.3.6.3.2 sram write timing with #ce4/#ce11 setup time
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6.4 sram read timings with #ce9 output disable time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 9 output disable time: none bclk a[24:0] #ce9 #ce x #rd d[15:0] #wait valid valid read cycle for another area valid figure ii.3.6.4.1 sram read timing with no #ce9 output disable time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 9 output disable time: 1 cycle bclk a[24:0] #ce9 #ce x #rd d[15:0] #wait valid valid output disable time read cycle for another area valid figure ii.3.6.4.2 sram read timing with #ce9 output disable time
ii bus modules: sram controller (sramc) ii-3-16 epson s1c33e08 technical manual ii.3.7 control register details table ii. 3.7.1 sramc register list address 0x00301500 0x00301504 0x00301508 0x0030150c 0x00301510 function sets bclk and #ce4/#ce11 setup time. sets static wait cycle for each area. sets device size for each area. sets device type for each area. sets area 6 location. register name bclk and setup time control register (psramc_bclk_setup) wait control register (psramc_swait) device size setup register (psramc_slv_size) device type setup register (psramc_a0_bsl) area location setup register (psramc_als) siz e 32 32 32 32 32 each sramc control register is described below. the sramc control registers are mapped to the 32 -bit device area at addresses 0x301500 to 0x301510 , and can be accessed in units of words, halfwords, or bytes. note : when setting the sramc control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301500: bclk and setup time control register (psramc_bclk_setup) name address register name bit function setting init. r/w remarks C ce9bclk ce9hold2 ce9hold1 ce9hold0 C ce11stup ce4stup bclk d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce9 area bclk divide control #ce9 area output disable time reserved #ce11 setup time #ce4 setup time bclk divide control C 1 0 0 0 C 0 0 1 C r/w r/w C r/w r/w r/w 0 when being read. 0 when being read. 00301500 (w) bclk and setup time control register (psramc_bclk _setup) 1 no setup tim e 0 +1 bclk C 0 to 7 C 1 no setup tim e 0 +1 bclk 1 sramc_clk 1/2 0 sramc_clk 1 1 sramc_clk 1/2 0 sramc_clk 1 d[31:8] reserved d7 ce9bclk: #ce9 area bclk divide control bit the bclk clock for the #ce 9 area is independent of other areas and is generated from the sramc_clk clock by being divided by 1 or 2. ce9 bclk is used to select this divide-by ratio. 1 (r/w): sramc_clk 1/2 (default) 0 (r/w): sramc_clk 1 d[6:4] ce9hold[2:0]: #ce9 area output disable time setup bits these bits select the output disable time for accessing the #ce 9 area. table ii. 3.7.2 setting the #ce9 output disable time ce9hold2 1 1 1 1 0 0 0 0 output disable cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle none ce9hold1 1 1 0 0 1 1 0 0 ce9hold0 1 0 1 0 1 0 1 0 (default: 0b000 = none) when using a device that has a long output disable time, set a delay time to ensure that no contention for the data bus occurs during the bus operation immediately after a device is read. d3 reserved d2 ce11stup: #ce11 setup time select bit this bit selects the setup time (#ce active to #rd/#wr ? active) for the #ce11 signal. 1 (r/w): no setup time 0 (r/w): +1 bclk (default) d1 ce4stup: #ce4 setup time select bit this bit selects the setup time (#ce active to #rd/#wr ? active) for the #ce4 signal. 1 (r/w): no setup time 0 (r/w): +1 bclk (default) d0 bclk: bclk divide control bit the bclk clock is used for sram areas except the #ce 9 area and is generated from the sramc_clk clock by being divided by 1 or 2 . bclk is used to select this divide-by ratio. note that the bclk pin output clock will not be divided; it is always the same as the sramc_clk clock. 1 (r/w): sramc_clk 1/2 (default) 0 (r/w): sramc_clk 1 use ce 9bclk (d7) to set bclk for the #ce9 area.
ii bus modules: sram controller (sramc) ii-3-18 epson s1c33e08 technical manual 0x301504: wait control register (psramc_swait) name address register name bit function setting init. r/w remarks C ce11wait2 ce11wait1 ce11wait0 ce10wait3 ce10wait2 ce10wait1 ce10wait0 ce9wait3 ce9wait2 ce9wait1 ce9wait0 ce8wait3 ce8wait2 ce8wait1 ce8wait0 ce7wait3 ce7wait2 ce7wait1 ce7wait0 ce6wait3 ce6wait2 ce6wait1 ce6wait0 ce5wait3 ce5wait2 ce5wait1 ce5wait0 ce4wait3 ce4wait2 ce4wait1 ce4wait0 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of #ce11 static wait cycles reserved number of #ce10 static wait cycles reserved number of #ce9 static wait cycles reserved number of #ce8 static wait cycles reserved number of #ce7 static wait cycles reserved number of #ce6 static wait cycles reserved number of #ce5 static wait cycles reserved number of #ce4 static wait cycles C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C r/w C r/w C r/w C r/w C r/w C r/w C r/w C r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301504 (w) wait control register (psramc_swait) C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 d31 reserved d[30:28] ce11wait[2:0]: number of #ce11 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 11 area. table ii. 3.7.3 setting the static wait cycle ce x w ait2 1 1 1 1 0 0 0 0 number of wait cyc les 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle no w ait cycle ce x w ait1 1 1 0 0 1 1 0 0 ce x w ait0 1 0 1 0 1 0 1 0 (default: 0b111 = 7 cycles) d27 reserved d[26:24] ce10wait[2:0]: number of #ce10 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 10 area. d23 reserved d[22:20] ce9wait[2:0]: number of #ce9 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 9 area. d19 reserved d[18:16] ce8wait[2:0]: number of #ce8 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 8 area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d15 reserved d[14:12] ce7wait[2:0]: number of #ce7 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 7 area. d11 reserved d[10:8] ce6wait[2:0]: number of #ce6 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 6 area. d7 reserved d[6:4] ce5wait[2:0]: number of #ce5 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 5 area. d3 reserved d[2:0] ce4wait[2:0]: number of #ce4 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 4 area.
ii bus modules: sram controller (sramc) ii-3-20 epson s1c33e08 technical manual 0x301508: device size setup register (psramc_slv_size) name address register name bit function setting init. r/w remarks C ce11size1 ce11size0 C ce9size1 ce9size0 ce8size1 ce8size0 ce7size1 ce7size0 ce6size1 ce6size0 ce5size1 ce5size0 ce4size1 ce4size0 d31C16 d15 d14 d13C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device size reserved #ce9 device size #ce8 device size #ce7 device size #ce6 device size #ce5 device size #ce4 device size C 0 1 C 0 1 0 1 0 1 0 1 0 1 0 1 C r/w C r/w r/w r/w r/w r/w r/w 0 when being read. 0 when being read. 00301508 (w) device size setup register (psramc_slv _size) C (see below) C ce xsize[1:0] size reserved 8 bits 16 bits reserved 11 10 01 00 d[31:16] reserved d[15:14] ce11size[1:0]: device size select bits these bits select the device size for the #ce 11 area. table ii. 3.7.4 selection of device size ce x size1 1 1 0 0 ce xsize0 1 0 1 0 de vice siz e reser ve d 8 bits 16 bits reser ve d connected data bu s C d[7:0] d[15:0] C (default: 0b01 = 16 bits) d[13:12] reserved note : the device size of the #ce 10 area is determined by the contents in address 0xc00000 at system boot. the device size is set to 16 bits when the lsb of the 0xc00000 contents is 0 or 8 bits when it is 1. d[11:10] ce9size[1:0]: device size select bits these bits select the device size for the #ce 9 area. d[9:8] ce8size[1:0]: device size select bits these bits select the device size for the #ce 8 area. d[7:6] ce7size[1:0]: device size select bits these bits select the device size for the #ce 7 area. d[5:4] ce6size[1:0]: device size select bits these bits select the device size for the #ce 6 area. d[3:2] ce5size[1:0]: device size select bits these bits select the device size for the #ce 5 area. d[1:0] ce4size[1:0]: device size select bits these bits select the device size for the #ce 4 area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30150c: device type setup register (psramc_a0_bsl) name address register name bit function setting init. r/w remarks C ce11type ce10type ce9type ce8type ce7type ce6type ce5type ce4type d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device type #ce10 device type #ce9 device type #ce8 device type #ce7 device type #ce6 device type #ce5 device type #ce4 device type C 0 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030150c (w) device type setup register (psramc_a0_bsl) C 1 bsl 0 a0 d[31:8] reserved d7 ce11type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce11 area. 1 (r/w): bsl 0 (r/w): a0 (default) table ii. 3.7.5 bus control signal pin functions in a0/bsl mode pin name #ce x #rd a0/#bsl #wrl/#wr #wrh/#bsh a0 (default) #ce x #rd unused #wrl #wrh bsl #ce x #rd #bsl #wr #bsh d6 ce10type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce10 area. 1 (r/w): bsl 0 (r/w): a0 (default) d5 ce9type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce9 area. 1 (r/w): bsl 0 (r/w): a0 (default) d4 ce8type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce8 area. 1 (r/w): bsl 0 (r/w): a0 (default) d3 ce7type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce7 area. 1 (r/w): bsl 0 (r/w): a0 (default) d2 ce6type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce6 area. 1 (r/w): bsl 0 (r/w): a0 (default) d1 ce5type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce5 area. 1 (r/w): bsl 0 (r/w): a0 (default) d0 ce4type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce4 area. 1 (r/w): bsl 0 (r/w): a0 (default)
ii bus modules: sram controller (sramc) ii-3-22 epson s1c33e08 technical manual 0x301510: area location setup register (psramc_als) name address register name bit function setting init. r/w remarks C a6loc d31C1 d0 reserved area 6 location setup C 0 C r/w 0 when being read. 00301510 (w) area location setup register (psramc_als) C 1 external 0 internal d[31:1] reserved d0 a6loc: area 6 location setup bit this bit selects area 6 location from between external area or internal area. 1 (r/w): external 0 (r/w): internal (default) note : the s1c33e08 does not support an external device to be used for area 6. do not set a6loc to 1.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.8 precautions the bclk pin output clock will not be divided regardless of how the bclk divide-by ratio is set using bclk (d0/0x301500 ); it is always the same as the sramc_clk clock. ? bclk : bclk divide control bit in the bclk and setup time control register (d0/0x301500)
ii bus modules: sram controller (sramc) ii-3-24 epson s1c33e08 technical manual this page is blank.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii. 4 sdram controller (sdramc) ii.4.1 sdram interface the sdram controller allows up to 64 mb of sdram to be connected directly to areas 7, 19 , and 22 . this section describes how to control the sdram interface, and how it operates. for instruction and data queue buffers to improve the sdram access performance and the bus arbiter to control sdram accesses from the cpu and lcdc, refer to section ii.4.2, instruction/data queue buffers, and section ii.4.3, bus arbiter, respectively. ii.4.1.1 overview of the sdram interface the following shows the main features and specifications of the sdram interface. ? up to 64mb sdram can be connected. ? three sdram areas (areas 7, 19, and 22 ) are reserved. sdram configuration examples - 32m 16-bit 1 chip (64mb) - 16m 16-bit 1 chip or 16m 8-bit 2 chips (32mb) - 8m 16-bit 1 chip or 8m 8-bit 2 chips (16mb) - 4m 16-bit 1 chip (8mb) - 2m 8-bit 2 chips (4mb) - 1m 16-bit 1 chip (2mb) ? data bus width: 16 bits ? cas latency: 1, 2, or 3 ? burst length: 2 ? supports 2 or 4 -bank sdram (ba1 and ba0 outputs). row address range: 2 k (sda10 Csda0), 4 k (sda11 Csda0), or 8 k (sda12 Csda0) column address range: 256 (sda7 Csda0), 512 (sda8 Csda0), or 1 k (sda9 Csda0) ? supports byte writes with the dqml and dqmh pins. ? supports bank interleaved access. ? incorporates a programmable 12 -bit auto refresh counter. the sdram can be refreshed as necessary, irrespective of the clock frequency used. ? intelligent self-refresh mode for low-power operation ? supports extended mode register set to program drive strength, temperature compensated self refresh, and partial array self refresh.
ii bus modules: sdram controller (sdramc) ii-4-2 epson s1c33e08 technical manual ii.4.1.2 sdramc pins table ii. 4.1.2.1 lists the pins used by the sdramc. table ii. 4.1.2.1 sdramc pin list pin name a[13:12] a[10:1] a[15:14] d[15:0] sd a10 sdcke sdclk #sdcs #sdras #sdcas #sd we dqml dqmh i/o o o o i/o o o o o o o o o o function address signal output pins (sd a[12:11]) address signal output pins (sd a[9:0]) bank select signal output pins (sdba[1:0]) data signal input/output pins (e xter nal data b us) address signal output pin (sd a10) sdram cloc k-enab le signal output pin sdram cloc k output pin sdram chip select signal output pin sdram ro w address strobe signal output pin sdram column address strobe signal output pin sdram wr ite signal output pin sdram data (to select lo w-order b yte) input/output mask signal output pin sdram data (to select high-order b yte) input/output mask signal output pin note : some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the sdramc. before the sdramc signals assigned to these pins can be used, the functions of these pins must be switched for the sdramc by setting each corresponding port function select register. for details of pin functions and how to switch over, see section i.3.3, switching over the multiplexed pin functions.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.1.3 configuration of sdram sdram area the #ce 7 area (area 7 , area 19 , or area 22 ) is reserved for the sdramc. however, the #ce 7 area is configured for an sram area controlled with the sramc and the sdramc is disabled at initial reset. therefore, to use an sdram, the #ce 7 area must be configured as the sdram area by setting sdon (d4/0x301600 ) and appon (d1/0x301610) to 1. ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) ? appon : sdapp control bit in the sdram application configuration register (d1/0x301610) note : when sdon (d4/0x301600) and appon (d1/0x301610) are set to 1, the #ce7 area external sram access conditions set in the sramc are disabled. setting sdram size and access conditions the table below lists the conditions related to sdram size and timing parameters that the sdramc can accommodate. table ii. 4.1.3.1 sdram setup items setup item sdram address configuration cas latency burst length t rp , t rcd t ras t rc , t rfc , t xsr content 32m 16 bits 1 16m 16 bits 1 8m 16 bits 1 4m 16 bits 1 1m 16 bits 1 (def ault) 16m 8 bits 2 8m 8 bits 2 2m 8 bits 2 3, 2 (def ault) or 1 2 (fix ed) 1 (def ault) to 4 cycles 1 (def ault) to 8 cycles 1 to 16 cycles (def ault: 15) contr ol bit settings addrc[2:0] (d[2:0]/0x301604) = 111 addrc[2:0] (d[2:0]/0x301604) = 011 addrc[2:0] (d[2:0]/0x301604) = 010 addrc[2:0] (d[2:0]/0x301604) = 001 addrc[2:0] (d[2:0]/0x301604) = 000 (def ault) addrc[2:0] (d[2:0]/0x301604) = 110 addrc[2:0] (d[2:0]/0x301604) = 101 addrc[2:0] (d[2:0]/0x301604) = 100 cas[1:0] (d[3:2]/0x301610) = 11, 10 (def ault) or 01 C t24ns[1:0] (d[13:12]/0x301604) = 00 (def ault) to 11 t60ns[2:0] (d[10:8]/0x301604) = 000 (def ault) to 111 t80ns[3:0] (d[7:4]/0x301604) = 0000 to 1110 (def ault) and 1111 sdram address configuration use addrc[ 2:0 ] (d[2:0]/0x301604 ) to select sdram size and chip configuration. this selection also sets up the bank size, column address size (page size), and row address size. ? addrc[2:0] : sdram address configuration bits in the sdram configuration register (d[2:0]/0x301604) table ii. 4.1.3.2 selecting sdram size sdram configuration 32m 16-bit 1 16m 8-bit 2 8m 8-bit 2 2m 8-bit 2 16m 16-bit 1 8m 16-bit 1 4m 16-bit 1 1m 16-bit 1 addrc2 1 1 1 1 0 0 0 0 addrc1 1 1 0 0 1 1 0 0 addrc0 1 0 1 0 1 0 1 0 bank 4 4 4 2 4 4 4 2 ro w 8k 4k 4k 2k 8k 4k 4k 2k column 1k 1k 512 512 512 512 256 256 memory siz e 64m b ytes 32m b ytes 16m b ytes 4m b ytes 32m b ytes 16m b ytes 8m b ytes 2m b ytes the relationship between the cpu addresses and the bank, colum n, and row addresses is shown below. a(m+n+p) bank address ro w address column address a(m+n+1) a(m+n) a(m+1) a(m) a1 a0 dqm figure ii.4.1.3.1 sdram address m: column address size (number of bits) 8 bits (256), 9 bits (512), or 10 bits (1k) n: row address size (number of bits) 11 bits (2k), 12 bits (4k), or 13 bits (8k) p: bank address size (number of bits) 1 bit (2 banks) or 2 bits (4 banks) when reading/writing byte data, the sdram controller decodes a 0 /bsl and wrh/bsh into dqml and dqmh. upper address bits that are not used (depending on memory size) are all set to 0s.
ii bus modules: sdram controller (sdramc) ii-4-4 epson s1c33e08 technical manual figures ii. 4.1.3.2 and ii.4.1.3.3 show examples of how to connect sdrams and figure ii.4.1.3.4 shows the area configuration and address ranges according to the sdram to be used. s1c33e08 a[15:14] a[13:12] sd a10 a[10:1] d[15:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 32m 16 bits (4 banks) ba[1:0] a[12:11] a10 a[9:0] dq[15:0] clk cke #cs #ras #cas #we dqmu dqml figure ii.4.1.3.2 example of connecting 64-mb sdram s1c33e08 a[15:14] a12 sd a10 a[10:1] d[15:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 8m 16 bits (4 banks) ba[1:0] a11 a10 a[9:0] dq[15:0] clk cke #cs #ras #cas #we dqmu dqml s1c33e08 a[15:14] a12 sd a10 a[10:1] d[15:8] d[7:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 8m 8 bits (4 banks) 2 ba[1:0] a11 a10 a[9:0] dq[7:0] clk cke #cs #ras #cas #we dqm ba[1:0] a11 a10 a[9:0] dq[7:0] clk cke #cs #ras #cas #we dqm figure ii.4.1.3.3 example of connecting 16-mb sdram
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x005fffff 0x00500000 0x004fffff 0x00400000 bank 1 bank 0 area 7 area 19 1m 16-bit 1 = 2mb (addrc[2:0] = "000") area 7 (2mb, 0x00400000C0x005fffff) area 19 (256mb, 0x10000000C0x1fffffff) 0x1fffffff 0x10200000 0x101fffff 0x10100000 0x100fffff 0x10000000 mirror bank 1 bank 0 1m 16-bit 1 = 2mb (addrc[2:0] = "000") 0x005fffff 0x00400000 bank 0 bank 1 area 7 area 19 2m 8-bit 2 = 4mb (addrc[2:0] = "100") bank 1 cannot be accessed. 0x1fffffff 0x10400000 0x103fffff 0x10200000 0x101fffff 0x10000000 mirror bank 1 bank 0 2m 8-bit 2 = 4mb (addrc[2:0] = "100") 0x005fffff 0x00400000 area 7 area 19 4m 16-bit 1 = 8mb (addrc[2:0] = "001") banks 1C3 cannot be accessed. 0x1fffffff 0x10800000 0x107fffff 0x10600000 0x105fffff 0x10400000 0x103fffff 0x10200000 0x101fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 area 19 0x1fffffff 0x11000000 0x10ffffff 0x10c00000 0x10bfffff 0x10800000 0x107fffff 0x10400000 0x103fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 area 19 0x1fffffff 0x12000000 0x11ffffff 0x11800000 0x117fffff 0x11000000 0x10ffffff 0x10800000 0x107fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 4m 16-bit 1 = 8mb (addrc[2:0] = "001") 0x005fffff 0x00400000 area 7 8m 16-bit 1 = 16mb (addrc[2:0] = "010") or 8m 8-bit 2 = 16mb (addrc[2:0] = "101") upper half of bank 0 and banks 1C3 cannot be accessed. bank 0 8m 16-bit 1 = 16mb (addrc[2:0] = "010") or 8m 8-bit 2 = 16mb (addrc[2:0] = "101") 16m 16-bit 1 = 32mb (addrc[2:0] = "011") or 16m 8-bit 2 = 32mb (addrc[2:0] = "110") upper par t of bank 0 and banks 1C3 cannot be accessed. 16m 16-bit 1 = 32mb (addrc[2:0] = "011") or 16m 8-bit 2 = 32mb (addrc[2:0] = "110") bank 3 bank 2 bank 1 bank 3 bank 2 bank 1 bank 0 bank 0 0x005fffff 0x00400000 bank 3 bank 2 area 7 bank 1 bank 0 area 19 0x1fffffff 0x14000000 0x13ffffff 0x13000000 0x12ffffff 0x12000000 0x11ffffff 0x11000000 0x10ffffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 32m 16-bit 1 = 64mb (addrc[2:0] = "111") upper par t of bank 0 and banks 1C3 cannot be accessed. 32m 16-bit 1 = 64mb (addrc[2:0] = "111") 0x005fffff 0x00400000 bank 3 bank 2 area 7 bank 1 bank 0 figure ii.4.1.3.4 sdram map
ii bus modules: sdram controller (sdramc) ii-4-6 epson s1c33e08 technical manual timing setup the following parameters can be set in conformity with sdram specifications before use. sdclk command sdba[1:0] sda[12:11, 9:0] sda10 dq[15:0] actv nop nop nop nop nop pre read ba ba ba row col row actv row ba row ba row row data data t rcd t rc t rp t ras cas latency nop actv ba bksel sdclk command sdcke sdba[1:0] sda[10] sda[12:11, 9:0] dq[15:0] self nop pall nop self refresh mode t rfc t xsr + 1 cycle t rp nop figure ii.4.1.3.5 sdram timing parameters ( 1 ) cas latency cas latency refers to the number of sdclk clocks until data is output from sdram after issuing the read command. for the sdramc s sdram interface, cas latency can be set from 1 to 3 using cas[1:0] (d[3:2]/0x301610). ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610) table ii. 4.1.3.3 cas latency settings cas1 1 1 0 0 cas latenc y 3 2 1 reser ve d cas0 1 0 1 0 when initially reset, cas latency is initialized to 2. ( 2) t rc , t rfc , t xsr t rc : active to active command cycle time t rfc : auto-refresh cycle time t xsr : exit self refresh to active command period these timing parameters can be set from 1 to 16 cycles (in sdclk) using t80ns[3:0] (d[7:4]/0x301604). ? t80ns[3:0] : number of t rc , t rfc and t xsr cycles setup bits in the sdram configuration register (d[7:4]/0x301604)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 4.1.3.4 t rc , t rfc and t xsr settings t80ns3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 t80ns2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 t rc , t rfc , t xsr 16 cycles 15 cycles 14 cycles 13 cycles 12 cycles 11 cycles 10 cycles 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t80ns1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 t80ns0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 when initially reset, t rc , t rfc and t xsr are initialized to 15 cycles. ( 3) t ras t ras : active to precharge command period this timing parameter can be set from 1 to 8 cycles (in sdclk) using t60ns[2:0] (d[10:8]/0x301604). ? t60ns[2:0] : number of t ras cycles setup bits in the sdram configuration register (d[10:8]/0x301604) table ii. 4.1.3.5 t r as settings t60ns2 1 1 1 1 0 0 0 0 t60ns1 1 1 0 0 1 1 0 0 t ras 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t60ns0 1 0 1 0 1 0 1 0 when initially reset, t ras is initialized to 1 cycle. ( 4) t rp , t rcd t rp : precharge to active command period t rcd : active to read or write delay time these timing parameters can be set from 1 to 4 cycles (in sdclk) using t 24 ns[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 301604 ). ? t24ns[1:0] : number of t rp and t rcd cycles setup bits in the sdram configuration register (d[13:12]/0x301604) table ii. 4.1.3.6 t r p and t rcd settings t24ns1 1 1 0 0 t24ns0 1 0 1 0 t rp , t rcd 4 cycles 3 cycles 2 cycles 1 cycle when initially reset, t rp and t rcd are initialized to 1 cycle.
ii bus modules: sdram controller (sdramc) ii-4-8 epson s1c33e08 technical manual ii.4.1.4 sdramc operating clock and sdram clock operating clock of the sdramc the sdramc is clocked by the following clocks generated by the cmu. for details on how to set and control the clocks, see section iii. 1, clock management unit (cmu). the sdramc operating clock supply to the sdramc is disabled by default setting. each clock supply can be controlled in the cmu. use the respective control bits to turn on only the required clocks to reduce the amount of power consumed on the chip. 1 . sdapp_cpu_clk clock this is the mclk clock used for interfacing between the cpu and sdramc. turn this clock on when using the sdramc. the clock supply can be controlled by sdapcpu_cke (d 6/0x301b00). ? sdapcpu_cke : sdramc cpu app clock control bit in the gated clock control register 0 (d6/0x301b00) furthermore, the sdapp_cpu_clk can automatically be stopped in halt mode. by setting sdapcpu_hcke (d 7/0x301b00 ) to 0 , the sdapp_cpu_clk stops when the cpu enters halt mode and it resumes when the cpu exits halt mode. ? sdapcpu_hcke : sdramc cpu app clock control (halt) bit in the gated clock control register 0 (d7/0x301b00) 2 . sdapp_lcdc_clk clock this is the mclk clock used for interfacing between the lcdc and sdramc. turn this clock on when using the sdram as the video ram. the clock supply can be controlled by sdaplcdc_cke (d 5/ 0x301b00). ? sdaplcdc_cke : sdramc lcdc app clock control bit in the gated clock control register 0 (d5/0x301b00) 3 . clocks for sdram interface and instruction/data queue buffers the sdramc inputs the osc_w clock (source clock for mclk) to operate the sdram interface. also this clock is used as sdclk (sdram synchronous clock). so the sdram can be accessed using a clock two times faster than the cpu clock when mclk is generated by dividing osc_w by 2. the osc_w clock supply can be controlled by sdapcpu_cke (d 6/0x301b00 ) and sdaplcdc_cke (d5/0x301b00). either one or both are set to 1, the osc_w clock is supplied to the sdramc. note : if the operating clock (sdclk) is stopped while the sdram is being accessed, a system failure may occur due to stoppage of the sdram operation in uncontrolled status. the following operations stop the sdclk, therefore, do not perform these operations when the sdram may be accessed. ? setting the s1c33e08 in sleep status ? switching the p21 port function from sdclk output to general-purpose input/output ? disabling the clock supply to the sdramc module besides the cpu, the dma controller (when dma transfer from/to the sdram is enabled) and the lcd controller (when sdram is configured as the vram for the lcdc) access the sdram. in this case, before performing an above operation, disable the dma transfer and the lcdc so that the sdram will not be accessed.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 4 . sdsapb_clk clock the sdsapb_clk is used to operate the sdramc control registers. to setup the registers, this clock is required. after the registers are set up, the clock supply can be stopped to reduce power consumption by setting sdsapb_cke (d4/0x301b00) to 0. ? sdsapb_cke : sdramc sapb i/f clock control bit in the gated clock control register 0 (d4/0x301b00) setting any of the clock control bits above (initially 0 ) to 1 turns on the corresponding clock supply to the sdramc. the sdramc operating clocks stop depending on the type of sta ndby mode. halt mode: the operating clock is supplied the same way as in normal mode. it can be stopped by setting the cmu register. sleep mode: the clock supply stops. therefore, the sdramc also stops operating in sleep mode. double frequency mode the sdramc supports double frequency mode in which the sdram can be operated with a clock two times faster than the cpu clock. for example, when the cpu runs with a 45 mhz clock, the sdram can be operated with a 90 mhz clock. to set the sdramc in double frequency mode: (1 ) configure mclk as osc_w 1/2. (2 ) set dbf (d5/0x301610) to 1. ? dbf : double frequency mode enable bit in the sdram application configuration register (d5/0x301610) note : the sdclk clock frequency is limited to 90 mhz, therefore, double frequency mode cannot be set when the cpu clock (mclk) is higher than 45 mhz. in this case (normal mode), a clock up to 60 mhz (cpu maximum operating frequency) can be used for the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-10 epson s1c33e08 technical manual ii.4.1.5 control and operation of sdram interface initializing sdram to use sdram, it must be initialized by following the procedure below after switching power on. 1 . setting sdram interface pins switch over the pins shared with general-purpose input/output ports or other peripheral functions for sdram use by setting the relevant port function select register. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. 2 . initializing the sdramc registers set up the sdramc registers in the following order: (1 ) sdram configuration register (0x301604) set sdram size/address-related parameters and access timing par ameters. (2 ) sdram refresh register (0x301608) set the auto-refresh and self-refresh counters. (3 ) sdram initial register (0x301600) set sdon (d 4) to 1 (sdramc enabled). (4 ) sdram application configuration register (0x301610) set cas latency and enable the sdapp and arbiter. also enable double frequency mode and instruction queue buffer if necessary. 3 . wait after sdram power-on after the power to sdram is turned on, the nop state (#sdcs = 1 ) must be maintained for a certain time (e.g., 100 s, 200 s or more). because this time varies with each sdram, refer to the specifications of the sdram being used. 4 . executing an sdram initial sequence in order to initialize the sdram, the pall (precharge all), ref (auto refresh), and mrs (mode register set) commands must be executed sequentially. note that the initialization sequence depends on the sdram. example 1 : pall ref ref mrs ( emrs) example 2 : pall mrs ref ref ( ref ref ref ref ref ref) refer to the specifications of the sdram to be used for the initialization sequence. each command can be executed using the control bit shown below. to execute the pall (precharge all) command: write 0x12 to the sdram initial register (0x301600); inipre (d1/0x301600) should be set to 1. then write any data to any address in the sdram. this dummy write is required as the trigger to send the pall command. ? inipre : pall command enable for initialization bit in the sdram initial register (d1/0x301600) to execute the ref (auto refresh) command: write 0x11 to the sdram initial register (0x301600); iniref (d0/0x301600) should be set to 1. then write any data to any address in the sdram. this dummy write is required as the trigger to send the ref command. ? iniref : ref command enable for initialization bit in the sdram initial register (d0/0x301600) when executing the ref command twice or more, insert the nop instruction between the executions. execute ref command execute nop execute ref command ( ref nop ref . . .) the sdram timing parameters set in the sdram configuration register ( 0x301604 ) is not effective in this manual initialization sequence. therefore, enough number of nop instructions must be executed to satisfy the sdram timings.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 to execute the mrs/emrs (mode register set/extended mode register set) command: write 0x14 to the sdram initial register (0x301600); inimrs (d2/0x301600) should be set to 1. then write any data to the specific address shown below according to the cas latency (mrs) or extended mode parameters (emrs). ? inimrs : mrs command enable for initialization bit in the sdram initial register (d2/0x301600) table ii. 4.1.5.1 data write address to execute the mrs/emrs command cpu address sdram address mrs cas latency = 1 cas latency = 2 cas latency = 3 emrs a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1 0 0 0 0 0 0 0 0 see sdram specifications . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 ba1 mod e rese rv ed te st mode cas latency wb burst length bt mod e reser ve d ds p asr tcsr ba0 sd a12 sd a11 sd a10 sd a9 sd a8 sd a7 sd a6 sd a5 sd a4 sd a3 sd a2 sd a1 sd a0 for example, to execute an mrs command with 2 of cas latency specified, write data (any value) to address 0x10000442 (when the sdram is mapped to area 19 ) after writing 0x14 to the sdram initial register ( 0x301600). notes : ? the cas latency specified in the mrs command must be the same as the cas[1:0 ] (d[3:2]/ 0x301610 ) set value. ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610) ? after the initial sequence commands are executed, the command enable bits must be set to 0 . write 0x10 to the sdram initial register (0x301600 ) after the last initialization command has been executed. ? the self-refresh function must be disabled until the sdram has finished initialization. 5. checking if the sdram has been initialized sden (d 3/0x301600 ) is reset to 0 after power-on, and is set to 1 upon completion of the initialization sequence shown above. make sure that sden (d 3/0x301600) is set to 1 before the sdram is accessed. in addition to being reset at power-on, sden (d 3/0x301600 ) is reset to 0 by writing 0 to sdon (d4/ 0x301600). ? sden : sdram initialize flag in the sdram initial register (d3/0x301600) ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) sdram power sdclk command sdcke #sdcs #sdras #sdcas #sdwe dqmh/dqml sdon bit inipre bit iniref bit inimrs bit sden bit sda10 sdba[1:0] sda[12:11, 9:0] pall nop nop nop nop h h ref ref mrs cmd valid valid valid valid valid 100 s min. t rp t rfc t rfc v cc(min. ) nop figure ii.4.1.5.1 sdram power-up and initialization
ii bus modules: sdram controller (sdramc) ii-4-12 epson s1c33e08 technical manual sdram commands the sdram is controlled by commands that are comprised of a combination of high or low logic level signals. table ii. 4.1.5.2 lists the commands output by the sdram controller. table ii. 4.1.5.2 list of the supported sdram commands function deselect bank activ e bank precharge precharge all wr ite read mode register set nop a uto refresh self refresh entr y self refresh exit data wr ite/output enab le data wr ite/output disab le symbol C a ctv pre p all writ read mrs nop ref self C C C sdcke h h h h h h h h h h l l h h h dqm (dqmh/l) x x x x x x x x x x x l h sdb a[1:0] x v v x v v x x x x x x x sd a10 x v l h l l v x x x x x x sd a[12:11] sda[9:0] x v x x v v v x x x x x x #sdcs h l l l l l l l l l h x x #sdras x l l l h h l h l l x x x #sdcas x h h h l l l h l l x x x #sd we x h l l l h l h h h x x x command pins v = valid, x = don t care, l = low level, h = high level because all of these commands are output by the sdram controller as necessary, they do not need to be controlled by the user program, except for initializing the sdram. bus operations of sdram the external data bus of the s 1c33e08 is 16 bits wide. depending on the device size and data size of the instruction executed, two or more bus operations may occur. table ii. 4.1.5.3 shows bus operations in the sdram area. table ii. 4.1.5.3 bus operations de vice siz e 16 bits data siz e byte half word w ord r/w w r w r w r v alid signal dqml dqmh read dqmh/l read dqmh/l read little endian d[15:8] pins C d[7:0] C d[7:0] d[7:0] pins d[7:0] C d[7:0] C access count 1 1 1 1 1 1 1st 2nd 1st 2nd a1 ? ? ? ? ? ? 0 1 0 1 a0 0 1 0 1 ? ? ? ? ? ? d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16]
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 read cycle the sdramc always reads data from the sdram in bursts. the burst length is fixed at 2. figure ii. 4.1.5.2 shows an example of timing chart when reading out 2 -word data from the same row address. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop pre nop read nop read ba ba row d(1-1) d(1-2) d(2-1) d(2-2) t rcd t rp cas latency cas latency row col1 ba col2 ba figure ii.4.1.5.2 burst read in the same page figure ii. 4.1.5.3 shows an example of a timing chart in cases where the row address is changed during burst read. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop nop pre nop read ba ba row1 d (n) d (n+1) d (0) d (1) t rcd t rp t rcd t rp cas latency cas latency row1 coln ba actv nop pre nop read ba ba row2 row2 col0 ba figure ii.4.1.5.3 changing row address during burst read
ii bus modules: sdram controller (sdramc) ii-4-14 epson s1c33e08 technical manual write cycle when writing to the sdram, data are always written in a single operation. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop pre nop read ba ba row1 d (n) d (n+1) d (m) t rcd t rp cas latency row1 coln ba writ pre ba colm ba figure ii.4.1.5.4 burst read to single write (same page) bank interleaved access multiple banks (up to four banks) can be activated at the same time. this makes it possible to access the sdram successively, one bank after another without issuing the actv (active) command. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] bank 1 bank 2 actv h nop nop actv read read read ba1 ba1 row2 d (n) d (n+1) t rp (bank 1 cannot be accessed) cas latency row2 row 1 row 1 active read precharge active read coln ba2 colm ba1 coll ba2 pre nop nop ba1 d (m) d (m+1) d (l) actv ba1 row3 row3 figure ii.4.1.5.5 bank interleaved access
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 sdram refresh the sdramc supports two sdram refresh modes: auto-refresh and self-refresh. auto-refresh the sdram controller incorporates a 12 -bit auto refresh counter. this counter continues counting on the sdclk clock edges, and when a specified count is reached, commands are sent to the sdram that precharges and auto-refreshes all banks. the counter is reset at that time, and starts counting for the next refresh period. the counter is also reset by self-refresh. the auto-refresh period is determined by the sdclk (mclk or double of mclk) clock frequency and the count value set in aurco[ 11:0] (d[11:0]/0x301608). ? aurco[11:0] : sdram auto-refresh counter bits in the sdram refresh register (d[11:0]/0x301608) for aurco[ 11:0 ] (d[11:0]/0x301608 ), set the appropriate value meeting the specifications of your sdram. the count value is obtained by the equation below. rfp aurco CCCCCCCC f clk - bl - cl - 2 t rp - t rcd - 3 rows rfp: maximum refresh period [s] rows: row address size f clk : sdclk clock frequency [hz] bl: burst length (= 2) cl: cas latency t rp : precharge command period [number of cycles] t rcd : active to read or write delay time [number of cycles] if rfp = 64 ms, rows = 4,096 , f clk = 20 mhz, cl = 2 , t rp = 2 , and t rcd = 2 , for example, the value to set is calculated as follows: 0.064 aurco CCCCCCCC 20,000,000 - 2 - 2 - 2 2 - 2 - 3 = 299 4,096 therefore, set any value equal to or less than 299 (0x12 b) for aurco[11:0] (d[11:0]/0x301608). sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] ref actv h l pall nop nop t rfc t rp figure ii.4.1.5.6 auto refresh
ii bus modules: sdram controller (sdramc) ii-4-16 epson s1c33e08 technical manual self-refresh self-refresh uses the sdram s self-refresh function and does not require clock pulses during the refresh period, thus helping to reduce the chip s power consumption. this self-refresh function is also used for data retention during power-down mode. to cause the sdram to be self-refreshed, set selen (d 23/0x301608 ) to 1 . this enables the sdram controller to send the self-refresh command (which sets the sdcke output to low) to the sdram. ? selen : sdram self-refresh enable bit in the sdram refresh register (d23/0x301608) the command is actually sent a certain time after accessing or auto-refreshing the sdram, so the sdram controller contains a self-refresh counter to count this time. the counter counts on sdclk clock edges, and when the designated count is reached, the sdram controller sends the self-refresh command to the sdram. when an sdram access or auto-refresh command is issued, the counter is reset and starts counting again. the designated value for the counter can be specified in a range of 1 to 127 by using the selco[6:0 ] (d[22:16]/ 0x301608). do not set the counter to 0 when the self-refresh function is enabled. ? selco[6:0] : sdram self-refresh counter bits in the sdram refresh register (d[22:16]/0x301608) when an sdram access occurs during self-refresh mode, sdcke is returned high and the sdram is taken out of self-refresh mode. after the sdram access has finished, the sdram controller sends another self- refresh command when the designated count is reached again. when the auto-refresh command is issued or an sdram access occurs, the counter will restart if the self- refresh command has not been sent to the sdram. therefore, the self-refresh counter value to be set must be smaller than the auto-refresh counter value. sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] seldo self l pall nop self refresh mode enters self refresh mode exits self refresh mode t rp the sdram clock stops when sckon = 0. figure ii.4.1.5.7 self refresh during self-refresh (while sdcke = low), the seldo (d 25/0x301608 ) remains 1 . therefore, it is possible to determine whether or not self-refresh is in operation by readi ng this status register. ? seldo : sdram self-refresh status bit in the sdram refresh register (d25/0x301608) furthermore, sdram clock output during self-refresh can be turned off in order to reduce the chip s power consumption by setting the sckon (d 24/0x301608) to 0. ? sckon : sdram clock enable during self-refresh bit in the sdram refresh register (d24/0x301608)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 power-down mode the s 1c33e08 supports two power-down modes for the c33 pe core (halt and sleep). halt mode ? the lcdc will be able to access the sdram in halt mode, if it is not disabled in normal mode. ? setting sdapcpu_cke (d6/0x301b00 ) and sdapcpu_hcke (d7/0x301b00 ) determines whether the cpu and dma will be able to access the sdram in halt mode or not. ? sdapcpu_cke : sdramc cpu app clock control bit in the gated clock control register 0 (d6/0x301b00) ? sdapcpu_hcke : sdramc cpu app clock control (halt) bit in the gated clock control register 0 (d7/0x301b00) table ii. 4.1.5.4 sdapp_cpu_clk clock status mode nor mal mode hal t mode sdapcpu_hcke x x x x 1 1 1 1 0 sdapcpu_cke 1 1 0 0 1 1 0 0 x sdaplcdc_cke 1 0 1 0 1 0 1 0 x sdram clock ( ? ) on (cpu , dma and lcdc) on (cpu and dma) on (lcdc) off (cannot be accessed) on (dma and lcdc) on (dma) on (lcdc) off (cannot be accessed) off (cannot be accessed) ? : ( ) indicates the modules that can access the sdram. note : to maintain data in the sdram during halt status with no sdram clock supplied, place the sdram in self-refresh mode by setting seldo (d25/0x301608) to 1 before stopping the sdram clock. sleep mode in sleep mode, the sdram can be turned off to reduce power consumption by the following procedure: 1 . if the cpu runs with the program stored in the sdram, it must be changed to a program located in the built-in ram or a memory other than the sdram. 2 . turn the sdram power off. 3 . switch the ports used for the sdram to general-purpose ports. 4 . drive the data and address buses to low. 5 . set sdon (d4/0x301600) to 0 to disable the sdramc. 6 . execute the slp instruction. ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) perform the following procedure when the cpu wakes up: 1 . the cpu wakes up from sleep status. 2 . configure the port functions for sdram. 3 . release the data and address buses from forced low driving. 4 . turn the sdram power on. 5 . wait 100 or 200 s for the sdram be stabilize according to the sdram specification. 6 . set sdon (d4/0x301600) to 1 to enable the sdramc. 7 . initialize the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-18 epson s1c33e08 technical manual ii.4.2 instruction/data queue buffers ii.4.2.1 overview the sdramc module contains the sdramc application unit that is an interface unit to connect between the c33 pe core (ahb bus) and the sdram interface unit described in section ii.4.1 . it generates the read, write, address, data, and handshake signals to drive the sdram interface unit. besides generating these signals, it also includes a data queue buffer and an instruction queue buffer to realize the instruction pre-fetch function and to increase the c33 pe core memory performance. sdram interface sdram queue buffer controller instruction queue buffer data queue buffer read/write control address register address to ahb bus data in data out read/write signals #wait address comparator sdramc application unit figure ii.4.2.1.1 instruction/data queue buffers ii.4.2.2 iqb (instruction queue buffer) this is a queue buffer to pre-fetch instructions and consists of 16 16 -bit d flip-flops. it is organized in 2 slots 8 16 bits as shown in the figure below. a[24:14] iqb address a[3:1] slot 0 slot 1 a[13:4] slot 0 address slot 1 address buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 figure ii.4.2.2.1 structure of iqb iqb acts as an instruction cache located between the cpu and sdram when it is enabled by setting iqb (d 0/ 0x301610) to 1. ? iqb : instruction queue buffer enable bit in the sdram application configuration register (d0/0x301610) when the cpu attempts to fetch the first instruction from the sdram after iqb is enabled, the sdramc ap - plication unit pre-fetches 8 instructions from the sdram (including cpu aimed instructions) and stores them in iqb's slot 0 . the cpu then gets the needed instruction from iqb. after that, the cpu can get the subsequent instructions to be executed from iqb if iqb contains them (called as iqb hit). if iqb does not contain the instruc - tion to be executed next (called as iqb not hit), the sdramc application unit pre-fetches another 8 instruc - tions (including cpu aimed instructions) from the sdram and stores them in iqb's slot 1 , then the cpu gets the needed instruction from iqb's slot 1 . the two slots are used alternately like this and the cpu continues fetching instructions from iqb while the routine to be executed is located in the sdram. each slot can store 8 instructions, so iqb always stores the pre-fetched data beginning with a 4 -word (128 bits) boundary address.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 cpu aimed instruction address a[3:1] 000 001 010 011 100 101 110 111 slot 0, 1 buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 cpu aimed instr uction iqb pre-f etched instr uction figure ii.4.2.2.2 instructions in slot when iqb is disabled (iqb (d 0/0x301610 ) = 0 ), the cpu can only fetch the instruction or data from the sdram through the data queue buffer described below. ii.4.2.3 dqb (data queue buffer) the dqb consists of two-stage 16 -bit buffers and is mainly used to store data read from the sdram and to decrease the sdram read latency. provided two stages, defined as buffer 0 and buffer 1 , correspond to two-burst reading for the sdram. when iqb (d 0/0x301610 ) is set to 1 to enable iqb, dqb acts as a data buffer in which data in the program is stored. when iqb (d 0/0x301610 ) is set to 0 to disable iqb, dqb acts as a pure read buffer in which all data read from the sdram are stored without distinction between instructions and data. note that dqb cannot be disabled. table ii. 4.2.3.1 lists the dqb status corresponding to the bus operation for the sdram. table ii. 4.2.3.1 dqb status corresponding to bus operation bus operation cpu instr uction f etch cpu v ector f etch cpu data read cpu data wr ite cpu stac k read cpu stac k wr ite dma data read dma data wr ite when iqb is disabled activ e activ e activ e inactiv e activ e inactiv e activ e inactiv e when iqb is enabled inactiv e activ e activ e inactiv e activ e inactiv e activ e inactiv e dqb status (active or inactive) the sdram interface always reads two successive half-word data beginning with a 32 -bit boundary address in burst reading. therefore, 16 -bit data at a word-boundary address (a[1:0 ] is corrected to 00 ) is always stored in buffer 0 , and the next read data at the subsequent half-word boundary address (a[1:0 ] = 10 ) is always stored in buffer 1. if dqb contains the needed data when the cpu reads data from the sdram, no sdram read cycle is generated and data is read from dqb.
ii bus modules: sdram controller (sdramc) ii-4-20 epson s1c33e08 technical manual ii.4.2.4 operations using iqb/dqb reading sdram data in order to judge the iqb/dqb hit or iqb/dqb not hit, the sdramc application unit has an address register that holds the address in which data is buffered into iqb/dqb and an address comparator for comparing between the cpu read address and the address register. the address comparator compares the sdram address being accessed from the cpu with the address data in the address register, and issues hit if they are matched or not hit if they are not matched. after an initial reset, the iqb/dqb and address register statuses are reset as empty. therefore, the cpu's first fetching/reading of the sdram always causes not hit. in the case of not hit: the internal wait signal is output to the c 33 pe core and the bus cycle enters a wait state. the sdramc application unit reads data from the sdram through the sdram interface and stores it into iqb or dqb. when the buffer is ready to read, the internal wait signal is negated and the bus cycle reads the data from the iqb or dqb. in the case of hit: no sdram access is generated and the cpu can fetch or read the instruction or data from iqb or dqb with no wait state inserted. writing data to sdram when the cpu writes data to the sdram, the internal wait signal input to the c 33 pe core is asserted until the sdram interface has finished writing to the sdram. if data is written to the address in which data has buffered in iqb or dqb, the related buffer data is flushed.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.3 bus arbiter ii.4.3.1 overview the sdramc contains a bus arbiter. when the lcdc uses the external sdram as the vram, the cpu and lcdc may access the sdram simultaneously. similarly, an external bus access from the sramc may occur while the lcdc is accessing the sdram. the bus arbiter arbitrates the ownership of the external bus in such cases. the priority of the bus masters is ( 1 ) lcdc, (2 ) dma, (3 ) cpu, and (4 ) sramc. note, however, that the lcdc cannot interrupt a long dma transfer unless the dma sequential access time is set using dmaacctime[ 3:0 ] (d [3:0]/0x30119e). ? dmaacctime[3:0] : idma and hsdma sequential access time setup bits in the dma sequential access time register (d[3:0]/0x30119e) ii.4.3.2 controlling the bus arbiter at initial reset, the bus arbiter is disabled. in this case, sdram requests from the cpu and bus requests from the sramc will be accepted but the lcdc cannot request to access the sdram. the bus arbiter must be enabled before the lcdc can access the sdram. set arbon (d 31/0x301610) to 1 to enable the bus arbiter. ? arbon : arbiter enable bit in the sdram application configuration register (d31/0x301610) when no sdram access from the lcdc occurs, such as when the lcdc uses ivram only, the bus arbiter can be disabled by setting arbon (d 31/0x301610) to 0 to reduce current consumption.
ii bus modules: sdram controller (sdramc) ii-4-22 epson s1c33e08 technical manual ii.4.4 control register details table ii. 4.4.1 sdramc register list address 0x00301600 0x00301604 0x00301608 0x00301610 function enables sdramc and controls initialization. sets sdram size and timing parameters. controls refresh. controls sdapp module. register name sdram initial register (psdramc_ini) sdram configuration register (psdramc_ctl) sdram refresh register (psdramc_ref) sdram application configuration register (psdramc_app) siz e 32 32 32 32 the following describes each sdramc control register. the sdramc control registers are mapped to the 32 -bit device area at addresses 0x301600 to 0x301610 , and can be accessed in units of words, half-words or bytes.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301600: sdram initial register (psdramc_ini) name address register name bit function setting init. r/w remarks C C sdon sden inimrs inipre iniref d31C5 d4 d3 d2 d1 d0 reserved sdram controller enable sdram initialize flag mrs command enable for init. pall command enable for init. ref command enable for init. C 0 0 0 0 0 C r/w r r/w r/w r/w 0 when being read. 00301600 (w) 1 initialized 0 not initialized 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram initial register (psdramc_ini) d[31:5] reserved d4 sdon: sdram controller enable bit this bit enable the sdram controller. 1 (r/w): enable 0 (r/w): disable (default) when sdon is set to 1 , the sdram controller activates and outputs the sdram clock from the sdclk pin. before setting sdon to 1 , the sdramc clocks must be supplied to the sdram controller. d3 sden: sdram initialize flag this bit indicates that the sdram has finished initialization (mode register set). 1 (r): initialized 0 (r): not initialized (default) sden is reset to 0 after power-on, and is set to 1 upon completion of the initialization sequence. make sure that sden is set to 1 before the sdram is accessed. d2 inimrs: mrs command enable for initialization bit this bit enables to output the mrs (mode register set) command for initialization sequence. 1 (r/w): enable 0 (r/w): disable (default) in order to initialize the sdram, the pall (precharge all), ref (auto refresh), and mrs (mode register set) commands must be executed sequentially. note that the initialization sequence depends on the sdram. refer to the specifications of the sdram to be used for the initialization sequence. example 1 : pall ref ref mrs ( emrs) example 2 : pall mrs ref ref ( ref ref ref ref ref ref) to execute the mrs/emrs (mode register set/extended mode register set) command, write 0x14 to this register (inimrs should be set to 1 ). then write any data to a specific address shown below according to the cas latency (mrs) or extended mode parameters (emrs). table ii. 4.4.2 data write address to execute the mrs/emrs command cpu address sdram address mrs cas latency = 1 cas latency = 2 cas latency = 3 emrs a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1 0 0 0 0 0 0 0 0 see sdram specifications . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 ba1 mod e rese rv ed te st mode cas latency wb burst length bt mod e reser ve d ds p asr tcsr ba0 sd a12 sd a11 sd a10 sd a9 sd a8 sd a7 sd a6 sd a5 sd a4 sd a3 sd a2 sd a1 sd a0 for example, to execute an mrs command with 2 of cas latency specified, write data (any value) to address 0x10000442 (when the sdram is mapped to area 19 ) after writing 0x14 to the sdram initial register ( 0x301600). note : the cas latency specified in the mrs command must be the same as the cas[1:0] (d[3:2]/ 0x301610) set value. ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610)
ii bus modules: sdram controller (sdramc) ii-4-24 epson s1c33e08 technical manual d1 inipre: pall command enable for initialization bit this bit enables to output the pall (precharge all) command for initialization sequence. 1 (r/w): enable 0 (r/w): disable (default) to execute the pall (precharge all) command, write 0x12 to this register (inipre should be set to 1). then write any data to any address in the sdram. this dummy write is required as the trigger to send the pall command. see inimrs (d 2) for initialization sequence. d0 iniref: ref command enable for initialization bit this bit enables to output the ref (auto refresh) command for i nitialization sequence. 1 (r/w): enable 0 (r/w): disable (default) to execute the ref (auto refresh) command, write 0x11 to this register (iniref should be set to 1). then write any data to any address in the sdram. this dummy write is required as the trigger to send the ref command. see inimrs (d2) for initialization sequence. when executing the ref command twice or more, insert the nop instruction between the executions. execute ref command execute nop execute ref command ( ref nop ref . . .) notes : ? the sdram timing parameters set in the sdram configuration register (0x301604) is not effective in this manual initialization sequence. therefore, enough number of nop instructions must be executed to satisfy the sdram timings. ? after the initial sequence commands are executed, the command enable bits must be set to 0. write 0x10 to the sdram initial register (0x301600) after the last initialization command has been executed. ? the self-refresh function must be disabled until the sdram has finished initialization.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301604: sdram configuration register (psdramc_ctl) name address register name bit function setting init. r/w remarks C t24ns[1:0] = 0 to 3 1 to 4 cycles C t60ns[2:0] = 0 to 7 1 to 8 cycles t80ns[3:0] = 0 to 15 1 to 16 cycles C C t24ns1 t24ns0 C t60ns2 t60ns1 t60ns0 t80ns3 t80ns2 t80ns1 t80ns0 C addrc2 addrc1 addrc0 d31C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of sdram t rp and t rcd cycles reserved number of sdram t ras cycles number of sdram t rc , t rfc and t xsr cycles reserved sdram address configuration C 0 0 C 0 0 0 1 1 1 0 C 0 0 0 C r/w C r/w r/w C r/w 0 when being read. 0 when being read. 0 when being read. 00301604 (w) 111 110 101 100 011 010 001 000 addrc[2:0] configuration 32m x 16 bits x 1 16m x 8 bits x 2 8m x 8 bits x 2 2m x 8 bits x 2 16m x 16 bits x 1 8m x 16 bits x 1 4m x 16 bits x 1 1m x 16 bits x 1 sdram configuration register (psdramc_ctl) d[31:14] reserved d[13:12] t24ns[1:0]: number of sdram t rp and t rcd setup bits these bits set t rp and t rcd sdram timing parameters. ? t rp precharge to active command period ? t rcd active to read or write delay time table ii. 4.4.3 t r p and t rcd settings t24ns1 1 1 0 0 t24ns0 1 0 1 0 t rp , t rcd 4 cycles 3 cycles 2 cycles 1 cycle (default: 0b00 = 1 cycle) d11 reserved d[10:8] t60ns[2:0]: number of sdram t ras setup bits these bits set t ras sdram timing parameters. ? t ras active to precharge command period table ii. 4.4.4 t r as settings t60ns2 1 1 1 1 0 0 0 0 t60ns1 1 1 0 0 1 1 0 0 t ras 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t60ns0 1 0 1 0 1 0 1 0 (default: 0b000 = 1 cycle)
ii bus modules: sdram controller (sdramc) ii-4-26 epson s1c33e08 technical manual d[7:4] t80ns[3:0]: number of sdram t rc , t rfc , and t xsr setup bits these bits set t rc , t rfc , and t xsr sdram timing parameters. ? t rc active to active command cycle time ? t rfc auto-refresh cycle time ? t xsr exit self refresh to active command period table ii. 4.4.5 t rc , t rfc and t xsr settings t80ns3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 t80ns2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 t rc , t rfc , t xsr 16 cycles 15 cycles 14 cycles 13 cycles 12 cycles 11 cycles 10 cycles 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t80ns1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 t80ns0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b1110 = 15 cycles) d3 reserved d[2:0] addrc[2:0]: sdram address configuration bits these bits selects sdram size and chip configuration. this selection also sets up the bank size, column address size (page size), and row address size. table ii. 4.4.6 selecting sdram size sdram configuration 32m 16-bit 1 16m 8-bit 2 8m 8-bit 2 2m 8-bit 2 16m 16-bit 1 8m 16-bit 1 4m 16-bit 1 1m 16-bit 1 addrc2 1 1 1 1 0 0 0 0 addrc1 1 1 0 0 1 1 0 0 addrc0 1 0 1 0 1 0 1 0 bank 4 4 4 2 4 4 4 2 ro w 8k 4k 4k 2k 8k 4k 4k 2k column 1k 1k 512 512 512 512 256 256 memory siz e 64m b ytes 32m b ytes 16m b ytes 4m b ytes 32m b ytes 16m b ytes 8m b ytes 2m b ytes (default: 0b000 = 2m bytes)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301608: sdram refresh register (psdramc_ref) name address register name bit function setting init. r/w remarks C 0x0 to 0x7f C seldo sckon selen selco6 selco5 selco4 selco3 selco2 selco1 selco0 C aurco11 aurco10 aurco9 aurco8 aurco7 aurco6 aurco5 aurco4 aurco3 aurco2 aurco1 aurco0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved sdram self-refresh status sdram clock during self-refresh sdram self-refresh enable sdram self-refresh counter reserved sdram auto-refresh counter C 0 0 0 1 1 1 1 1 1 1 C 0 0 0 0 1 0 0 0 1 1 0 0 C r r/w r/w r/w C r/w 0 when being read. 0 when being read. 00301608 (w) 1 refresh mode 0 done 1 enabled 0 disabled 1 enabled 0 disabled sdram refresh register (psdramc_ref) C 0x0 to 0xfff d[31:26] reserved d25 seldo: sdram self-refresh status bit this bit indicates the sdram self-refresh status. 1 (r): in self-refresh mode 0 (r): not in self-refresh mode (default) seldo is 1 while the sdramc holds the sdcke pin low (i.e., the sdram is in self-refresh mode). otherwise, seldo = 0. before entering sleep mode, always be sure to read this bit using a program stored elsewhere (i.e., not in the sdram) to confirm that the sdram is in self-refresh mode. d24 sckon: sdram clock enable during self-refresh bit this bit selects whether to stop the sdram clock during self-re fresh or not. 1 (r/w): enable (not stopped) 0 (r/w): disable (stopped) (default) writing 0 to sckon causes the sdram clock output from the sdclk pin to stop and to remain off while the sdram is self-refreshed. this helps to reduce the chip's current consumption. if sckon = 1 , the sdram clock is always output from the sdclk pin even while the sdram is self-refreshed. d23 selen: sdram self-refresh enable bit this bit enable the sdram's self-refresh control function. 1 (r/w): enable 0 (r/w): disable (default) writing 1 to selen enables the sdramc to start self-refreshing the sdram (by setting sdcke output low). note that self-refreshing of the sdram actually begins a certain time after accessing or auto-refreshing the sdram. the duration of this elapsed time is defined by the number of clock cycles in selco[6:0] (d[22:16]). selen = 0 disables the self-refresh function.
ii bus modules: sdram controller (sdramc) ii-4-28 epson s1c33e08 technical manual d[22:16] selco[6:0]: sdram self-refresh counter bits these bits are used to set the self-refresh counter value. (default: 0x7f) if selen (d 23 ) is set to 1 (self-refresh-enabled), the self-refresh counter starts counting up on the sdclk clock edges beginning with 0 after accessing or auto-refreshing the sdram. when the count specified here is reached, the sdcke output is pulled low, causing the sdram to start self-refreshing. if an access to the sdram occurs during self-refresh mode, sdcke is returned high, thereby taking the sdram out of self-refresh mode. d[15:12] reserved d[11:0] aurco[11:0]: sdram auto-refresh counter bits these bits are used to set the auto refresh counter value. (default: 0x8c) the auto-refresh counter counts up on the sdclk clock edges beginning with 0 , and when the count specified here is reached, the sdram controller sends an auto-refresh command. the counter is reset at that point, and starts counting the next refresh period. the counter is also reset by self-refresh. the value calculated from the equation below is the maximum count that can be set. rfp aurco CCCCCCCC f clk - bl - cl - 2 t rp - t rcd - 3 rows rfp: maximum refresh period [s] rows: row address size f clk : sdclk clock frequency [hz] bl: burst length (= 2) cl: cas latency t rp : precharge command period [number of cycles] t rcd : active to read or write delay time [number of cycles]
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301610: sdram application configuration register (psdramc_app) name address register name bit function setting init. r/w remarks C arbon C dbf incr cas1 cas0 appon iqb d31 d30C6 d5 d4 d3 d2 d1 d0 arbiter enable reserved double frequency mode enable incr transfer enable cas latency setup sdapp control instruction queue buffer enable 0 C 0 0 1 0 0 0 r/w C r/w r/w r/w r/w r/w 0 when being read. 00301610 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram application configuration register (psdramc_app) 1 on 0 off 1 enabled 0 disabled cas[1:0] cas latency 3 2 1 reserved 11 10 01 00 d31 arbon: arbiter enable bit this bit enables the bus arbiter. 1 (r/w): enable 0 (r/w): disable (default) when arbon is set to 1 , the bus arbiter is enabled and can arbitrate the sdram access requests from the cpu, lcdc, and sramc. when arbon is set to 0 , the bus arbiter is disabled. in this case, the lcdc cannot access the sdram. d[30:6] reserved d5 dbf: double frequency mode enable bit this bit enables double frequency mode. 1 (r/w): enable 0 (r/w): disable (default) when dbf is set to 1 , the sdramc can use the sdram clock (90 mhz max.) two times faster than the cpu clock ( 45 mhz max.). set dbf to 0 when the sdramc clock frequency is the same as the cpu operating clock (60 mhz max.). d4 incr: incr transfer enable bit this bit enables incr transfer. when incr is set to 1 , the sdramc will enhance the speed of data reading from the sdram by the lcdc and idma. 1 (r/w): enable 0 (r/w): disable (default) d[3:2] cas[1:0]: cas latency setup bits these bits set cas latency. cas latency refers to the number of sdclk clocks until data is output from sdram after issuing the read command. table ii. 4.4.7 cas latency settings cas1 1 1 0 0 cas latenc y 3 2 1 reser ve d cas0 1 0 1 0 (default: 0b10 = 2) d1 appon: sdram application unit control bit this bit turns the sdram application unit on and off. 1 (r/w): on 0 (r/w): off (default) appon must be set to 1 when using the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-30 epson s1c33e08 technical manual d0 iqb: instruction queue buffer enable bit this bit enables the iqb (instruction queue buffer). 1 (r/w): enable 0 (r/w): disable (default) setting iqb to 1 enables iqb and instructions stored in the sdram are pre-fetched into the iqb. the iqb acts as a high-speed instruction cache for the cpu. in this case, dqb is used as a data read buffer. when iqb is set to 0 , iqb is disabled and dqb is used as an instruction/data buffer.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.5 precautions if the operating clock (sdclk) is stopped while the sdram is being accessed, a system failure may occur due to stoppage of the sdram operation in uncontrolled status. the following operations stop the sdclk, therefore, do not perform these operations when the sdram may be accessed. ? setting the s1c33e08 in sleep status ? switching the p21 port function from sdclk output to general-purpose input/output ? disabling the clock supply to the sdramc module besides the cpu, the dma controller (when dma transfer from/to the sdram is enabled) and the lcd controller (when sdram is configured as the vram for the lcdc) access the sdram. in this case, before performing an above operation, disable the dma transfer and the lcdc so that the sdram will not be accessed.
ii bus modules: sdram controller (sdramc) ii-4-32 epson s1c33e08 technical manual this page is blank.
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual iii peripheral modules 1 (system)
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1 clock management unit (cmu) iii.1.1 overview of the cmu the clock management unit (cmu) controls the operating clock supplied to each functional module. the main functions of the cmu are outlined below. ? controls reset and nmi inputs ? selects the system clock source (osc3, pll, or osc1) ? controls on/off of the osc3 and osc1 oscillator circuits ? controls on/off and frequency multiplication rate of the pll ? controls sscg ? clock control corresponding to standby modes (sleep and halt) ? selects divide ratio of the main system clock ? selects an external bus clock ? controls on/off of clock supply for each functional module through system clock selection, oscillator circuit, and pll control, and main system clock divide ratio selection and clock on/off control for each functional module, the cmu enables the most suitable operating clock frequency to be selected for the processing involved, as well as to turn off unnecessary clock supply, which combined with standby mode, helps to significantly reduce power consumption on the chip. osc/pll/ sscg control osc3 oscillator (48 mhz) divider (1/1C1/32) divider (1/1C1/10) osc1 oscillator (32.768 khz) reset/nmi control pll x1Cx16 (20C90 mhz) clock switch nmi reset cmu #nmi #reset mclki mclko osc3 pllin_div osc oscsel mclkdiv cmu_clksel 11 clocks sleep wakeup, etc. halt osc_w osc3_div pll osc1 mclk clock on/off control to peripheral modules clock on/off control in halt mode power down control to ahb bus and some peripheral modules clock on/off control to sdramc to c33 pe core clock on/off control to lcdc cmu_clk clock on/off control to usb to rtc rtc_clki rtc_clko divider (1/1C1/16) 1/2 sscg figure iii.1.1.1 cmu block diagram note : the cmu control registers at addresses 0x301b00C0x301b14 are write-protected. before the cmu control registers can be rewritten, write protection of these registers must be removed by writing data 0x96 to the clock control protect register (0x301b24). note that since unnecessary rewrites to addresses 0x301b00C0x301b14 could lead to erratic system operation, the clock control protect register (0x301b24) should be set to other than 0x96 unless said cmu control registers must be rewritten.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-2 epson s1c33e08 technical manual iii.1.2 reset input and initial reset the cmu also has a function to generate an internal reset signa l from external reset input (#reset). iii.1.2.1 initial reset pin the #reset pin is used for initial reset input from outside the ic. set the #reset pin to 0 (low) to reset the ic. the #reset input signal is sampled with the osc 3 clock. therefore, the chip cannot be reset when the osc3 clock is not input or generated. moreover, to assert the internal reset signal #reset = 0 must be continuously detected at least three times in this sampling. the #reset signal should be held low for at least three osc 3 clock cycles to confirm that the chip is reset. also the internal reset signal is negated when #reset = 1 (high) is continuously detected three times. the s 1c33e08 is reset by the low state (= 0 ) on the internal reset signal, and starts operating when the reset signal is released back to high (= 1). osc3 clock #reset internal reset signal 3 cycles 2 cycles or less 3 cycles reset state figure iii.1.2.1.1 #reset sampling iii.1.2.2 initial reset status the c 33 pe core and internal peripheral circuits are initialized while the internal reset signal is kept 0 . the following shows the internal reset status: cpu ttbr: initialized to 0xc00000 cpu pc: the reset vector at address 0xc00000 is loaded to the pc. cpu psr: all the psr bits are reset to 0. other cpu registers: undefined cpu operating clock: the cpu operates with the osc3 1/1 clock. oscillator circuit: both the high-speed (osc 3 ) and low-speed (osc1 ) oscillator circuits are turned on (pll and sscg are turned off). clock supply to peripheral modules: all clocks are enabled except for the usb, sdramc, and lcdc. i/o pin status: initialized (see section i.3.2, pin functions. ) other peripheral modules: initialized or undefined (see each i/o map.) note : the s1c33e08 does not support a hot reset feature that maintains i/o pin status and the ttbr value.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.2.3 power-on reset when turning on the power for the chip, always be sure to cold reset the chip to ensure that it will start operating normally. since the #reset pin is a gate input, a power-on reset circuit should be configured external to the chip. initial reset (#reset = 0 ) causes the high-speed (osc3 ) oscillator circuit to start oscillating, and when the reset signal is released back high, the cpu starts operating with the osc 3 clock. the high-speed (osc3 ) oscillator circuit requires a finite time until its oscillation stabilizes after it starts operating. to confirm that the cpu is started, the initial reset can only be deasserted after this oscillation stabilization time elapses. note : the oscillation start time of the high-speed (osc3) oscillator circuit varies with the device used, board patterns, and operating environment. therefore, sufficient time should be provided before the reset signal is deasserted. power-on sequence to ensure that the chip will operate normally, observe the timing requirements given below when turning on the power for the chip. i/o power voltage v ddh , av dd internal power voltage v dd , plv dd osc3 #reset v dd min. t vdd t sta3 t rst figure iii.1.2.3.1 power-on sequence (1) t vdd : the time until the power supply for the chip stabilizes after being turned on. turn on the power supplies in order of the following (or at the same time): internal core power supply (v dd , plv dd ) i/o power supply (v ddh , av dd ) input signal applied (2) t sta 3 : osc 3 oscillation start time (3) t rst : minimum reset pulse width make sure #reset is held low (= 0 ) for at least 3 clock cycles after the osc3 clock supplied to the cmu has stabilized.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-4 epson s1c33e08 technical manual iii.1.2.4 precautions to be taken during initial reset core cpu when initially reset, all internal registers of the core cpu (except psr) become unstable. therefore, these registers must be initialized in a program. in particular, the stack pointer (sp) should always be initialized before accessing the stack. note that nmi requests are masked in hardware until data is written to the sp after initial reset, to prevent erratic operation. internal ram the content of internal ram becomes unstable when initially reset. internal ram must be initialized as required. high-speed (osc3 ) oscillator circuit when initially reset, the high-speed (osc 3 ) oscillator circuit starts oscillating, and when the reset signal is deasserted, the cpu starts operating with the osc 3 clock. to prevent erratic operation due to an instable clock when the chip is reset at power-on or while the high-speed (osc 3 ) oscillator circuit is idle, the reset signal should not be deasserted until after oscillation stabilizes. low-speed (osc 1 ) oscillator circuit when the chip is reset at power-on or while the low-speed (osc 1 ) oscillator circuit is idle, the low-speed (osc1 ) oscillator circuit also starts oscillating. the low-speed (osc1 ) oscillator circuit requires a longer time for oscillation to stabilize than the high-speed (osc 3 ) oscillator circuit. (see the electrical characteristics table.) to prevent erratic operation due to an instable clock, the osc 1 clock should not be used until after this stabilization time elapses. input/output ports and input/output pins initial reset initializes the control and data registers of the input/output ports, therefore, be set up back again in a program. other internal peripheral circuits the control and data registers of other peripheral circuits are initialized or made unstable by initial reset. therefore, these registers should be set up as required in a program. for details on how peripheral circuits are initialized by initial reset, see each i/o map or circuit description.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.3 nmi input the external nmi signal is input from the #nmi pin to the cmu, then forwarded to the cpu. for details about nmi exception handling by the cpu, refer to the s 1c33 family c33 pe core manual. notes : ? at least a 3 -system clock width of low pulse is required to generate nmi. after the nmi signal falls, maintain it at a low level for 3 or more clock cycles. ? nmi cannot be nested. the cpu keeps nmi input masked out until the reti instruction is executed after an nmi exception occurred.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-6 epson s1c33e08 technical manual iii.1.4 selecting the system clock source the cmu has the following three clock inputs, one of which can be selected as the source clock (osc) for the system. 1 . osc3 clock this clock is generated by the osc 3 oscillator circuit or supplied from an external source through the mclki pin. for details about the osc 3 oscillator circuit, see section iii.1.5.1, osc3 oscillator circuit. 2 . osc1 clock this is the source clock ( 32.768 khz, typ.) for the real time clock (rtc). when high-speed operation is unnecessary, this low-speed clock may be used to operate the system, thus helping to reduce power consumption on the chip. for details about the osc 1 oscillator circuit, see section iii.1.5.3, osc1 oscillator circuit. 3 . pll clock this is the pll output clock through the sscg module. the pll multiplies the osc 3 divided clock frequency by a given value to generate a clock for high-speed operation. the frequency multiplication rate can be set to one from 1 to 16 , note, however, that it depends on the osc3 divided clock frequency (maximum output frequency is 90 mhz). for details about the pll, see section iii. 1.6, controlling the pll. the clock source can be selected as shown in table iii. 1.4.1 by using oscsel[1:0] (d[3:2]/0x301b08). ? oscsel[1:0] : osc clock select bits in the system clock control register (d[3:2]/0x301b08) table iii. 1.4.1 selection of the system clock source oscsel1 1 1 0 0 oscsel0 1 0 1 0 cloc k sour ce pll osc3 osc1 osc3 (default: 0b00 = osc3) the clock source changed here is not reflected until after the cpu returns from sleep mode. therefore, the slp instruction must be executed once after setting oscsel[ 1:0 ] (d[3:2]/0x301b08 ). although the cpu returns from sleep mode to normal operation by an external interrupt from a port, for example, several functions are provided for use in clock source changes, thus automatically returning the cpu from sleep mode a certain time after slp instruction execution or leaving the osc 3 oscillator circuit turned on during sleep mode. section iii. 1 . 11 , standby modes, describes these methods of control in detail. note : when clock sources are changed, the cmu control registers must be set so that the cmu is supplied with a clock from the selected clock source upon returning from sleep mode immediately after the change. otherwise, the chip does not restart after the return from sleep mode.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.5 controlling the oscillator circuit iii.1.5.1 osc3 oscillator circuit the osc 3 oscillator circuit generates the main clock with which to operate the c 33 pe core and internal peripheral circuits. input/output pins of the osc3 oscillator circuit table iii. 1.5.1.1 lists the input/output pins of the osc3 oscillator circuit. table iii. 1.5.1.1 input/output pins of the osc3 oscillator circuit pin name mclki mclk o i/o i o function osc3 oscillator input pin: cr ystal/ceramic oscillator or e xter nal cloc k input osc3 oscillator output pin: cr ystal/ceramic oscillator (left open when using e xter nal cloc k input) structure of the oscillator circuit the osc 3 oscillator circuit accommodates a crystal/ceramic oscillator and external clock input. the core voltage v dd supplies power for this circuit. figure iii. 1.5.1.1 shows the structure of the osc3 oscillator circuit. oscillation circuit control signal sleep control oscillation circuit control signal sleep control v ss mclko mclki c d3 c g3 x'tal3 or ceramic osc3 mclko mclki external clock n.c. v ss v dd osc3 (1) crystal/ceramic oscillation circuit (2) external clock input r f r d figure iii.1.5.1.1 osc3 oscillator circuit for use as a crystal or ceramic oscillator circuit, connect a crystal (x tal3 ) or ceramic resonator and a feedback resistor (r f ), two capacitors (c g3 , c d3 ) and, if necessary, a drain resistor (r d ) to the mclki and mclko pins and v ss . to use an external clock, leave the mclko pin open and input a v dd -level clock (with a 50 % duty cycle) to the mclki pin. the range of oscillation frequencies is as follows: ? crystal oscillator: 5 mhz (min.) to 48 mhz (max.) ? ceramic oscillator: 48 mhz fixed ? external clock input: 5 mhz (min.) to 48 mhz (max.) ? a 48 mhz clock source with 0.25 % of accuracy should be connected for using the usb function. for details of oscillation characteristics and external clock input characteristics, see electrical characteristics. oscillation control cmu register control bit sosc 3 (d1/0x301b08) is used to control osc3 oscillation. ? sosc3 : high-speed oscillation (osc3) on/off control bit in the system clock control register (d1/0x301b08) setting this control bit to 0 causes the osc3 oscillator circuit to stop; setting it to 1 causes the osc3 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. when initially reset, this bit is set to 1 for enabling osc3 oscillation. note : when the oscillator is made to start oscillating by setting sosc3 (d1/0x301b08) from 0 to 1, a finite time is required until oscillation stabilizes (see electrical characteristics). to prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-8 epson s1c33e08 technical manual iii.1.5.2 setting the osc3 divider an osc 3 divided clock can be used as the system clock when osc3 is selected as the system clock source. setting the system clock to the lowest frequency possible according to the processing can reduce current consumption. the osc 3 divider generates six kinds of clocks from osc3?1/1 to osc3?1/32 . select a divided clock from those six clocks using osc3div[2:0] (d[10:8]/0x301b08). ? osc3div[2:0] : osc3 clock divider select bits in the system clock control register (d[10:8]/0x301b08) table iii. 1.5.2.1 selecting an osc3 divided clock osc3div2 1 1 1 1 0 0 0 0 osc3div1 1 1 0 0 1 1 0 0 cmu_clk osc3?1/1 osc3?1/1 osc3?1/32 osc3?1/16 osc3?1/8 osc3?1/4 osc3?1/2 osc3?1/1 osc3div0 1 0 1 0 1 0 1 0 (default: 0b000 = osc3?1/1) a divided clock can be selected at any time. however, up to 32 osc3 clock cycles are required before the clocks are actually changed after altering the register values. iii.1.5.3 osc1 oscillator circuit the s 1c33e08 contains an oscillator circuit (osc1 ) used to generate a 32.768 khz (typ.) clock as the clock source for timekeeping operation of the rtc. the osc1 clock can also be used as a power-saving operating clock for the core system or peripheral circuits. input/output pins of the osc1 oscillator circuit table iii. 1.5.3.1 lists the input/output pins of the osc1 oscillator circuit. table iii. 1.5.3.1 input/output pins of the low-speed (osc1) oscillator circuit pin name r tc_clki r tc_clk o i/o i o function osc1 input pin: cr ystal oscillator or e xter nal cloc k input osc1 output pin: cr ystal oscillator output (left open when e xter nal cloc k is input) structure of the osc1 oscillator circuit the osc 1 oscillator circuit accommodates a crystal oscillator and external clock input. the core voltage v dd supplies power for this circuit. figure iii. 1.5.3.1 shows the structure of the osc1 oscillator circuit. low level oscillation circuit control signal oscillation circuit control signal osc1 rtc_clko rtc_clki external clock n.c. v ss v dd osc1 (1) crystal oscillation circuit v ss rtc_clko rtc_clki oscillation circuit control signal (3) when not used (2) external clock input v ss rtc_clko rtc_clki c d1 c g1 x'tal1 r f r d figure iii.1.5.3.1 osc1 oscillator circuit
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 for use as a crystal oscillator circuit, connect a crystal resonator x tal 1 ( 32 . 768 khz, typ.), feedback resistor (r f ), two capacitors (c g1 , c d1 ), and, if necessary, a drain resistor (r d ) to the rtc_clki and rtc_clko pins and v ss , as shown in figure iii. 1.5.3.1 (1). to use an external clock, leave the rtc_clko pin open and input a v dd level clock (whose duty cycle is 50 %) to the rtc_clki pin. do not input v ddh or other i/o level clocks. the oscillator frequency/input clock frequency is 32.768 khz (typ.). make sure the crystal resonator or external clock used in the rtc has this clock frequency. with any other clock frequencies, the rtc cannot be used for timekeeping purposes. for details of oscillation characteristics and the input characteristics of external clock, see electrical characteristics. when not using the osc 1 oscillator circuit, connect the rtc_clki pin to v ss and leave the rtc_clko pin open. oscillation control internal control bit sosc 1 (d0/0x301b08 ) of the cmu register is used to control osc1 oscillation. ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) setting this control bit to 0 causes the osc1 oscillator circuit to stop; setting it to 1 causes the osc1 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. when initially reset, this bit is set to 1, so that the osc1 oscillator circuit continues oscillating. note : when the oscillator is made to start oscillating by setting sosc1 (d0/0x301b08) from 0 to 1, a finite time (of up to 3 seconds) is required until oscillation stabilizes. to prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-10 epson s1c33e08 technical manual iii.1.6 controlling the pll the pll multiplies the osc 3 clock frequency by a given value to generate a source clock for high-speed operation. iii.1.6.1 on/off control of the pll pllpowr (d 0/0x301b0 c) can be used to turn the pll on or off. ? pllpowr : pll on/off control bit in the pll control register (d0/0x301b0c) setting pllpowr (d 0/0x301b0 c) to 1 initiates pll operation. when initially reset, pllpowr (d0/0x301b0c) is set to 0 (power-down mode), with the pll turned off. note : immediately after the pll is started by setting pllpowr (d0/0x301b0c) to 1, an output clock stabilization wait time is required (e.g., 200 s in the s1c33e08). when the clock source for the system is switched over to the pll, allow for this wait time after the pll has turned on. iii.1.6.2 selecting the pll input clock the pll input clock can be selected from among 10 kinds of osc3 divided clocks, osc3?1/1 to osc3?1/10, using pllindiv[3:0] (d[23:20]/0x301b08). ? pllindiv[3:0] : pll input clock source divider select bits in the system clock control register (d[23:20]/0x301b08) table iii. 1.6.2.1 selecting the pll input clock pllindiv3 1 1 0 0 0 0 0 0 0 0 pllindiv2 0 0 1 1 1 1 0 0 0 0 pll input c loc k osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 osc3?1/8 pllindiv1 0 0 1 1 0 0 1 1 0 0 pllindiv0 1 0 1 0 1 0 1 0 1 0 other (default: 0b0111 = osc3?1/8) notes : ? the pll input clock can only be selected when the pll is turned off (pllpowr (d0/ 0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[1:0 ] (d[3:2]/0x301b08) = 0C2 ). if the pll input clock is changed while the system is operating with the pll clock, the system may operate erratically. ? for the range of the input clock frequency, see electrical characteristics.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.6.3 setting the frequency multiplication rate the pll frequency multiplication rate can be specified as shown in table iii. 1.6.3.1 by using plln[3:0 ] (d[7:4]/ 0x301b0c). ? plln[3:0] : pll multiplication rate setup bits in the pll control register (d[7:4]/0x301b0c) table iii. 1.6.3.1 pll frequency multiplication rates plln3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 plln2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 multiplication rate x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 plln1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 plln0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = x1) pll output clock frequency = pll input clock frequency multiplication rate notes : ? the frequency multiplication rate must be set so that the pll output clock frequency does not exceed the upper-limit operating clock frequency. for the multiplication rates that can be set and the range of the output clock frequency, see electrical characteristics. ? the frequency multiplication rate can only be set when the pll is turned off (pllpowr (d0/ 0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[1:0 ] (d[3:2]/0x301b08) = 0C2 ). if the frequency multiplication rate is changed while the system is operating with the pll clock, the system may operate erratically.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-12 epson s1c33e08 technical manual iii.1.6.4 other pll settings v-divider to ensure that frequency f vco obtained by |